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www.latticesemi.com 1 ispm4k_15z ispmach 4000v/b/c/z family 3.3v/2.5v/1.8v in-system programmable superfast high density plds ju ly 2003 data sheet tm tm ? 2003 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci cations and information herein are subject to change without notice. new! industry?s lowest po wer cplds! ispmach 4000 z features high performance ?f max = 400mhz maximum operating frequency ?t pd = 2.5ns propagation delay ? up to four global clock pins with programmable clock polarity control ? up to 80 pts per output ease of design ? enhanced macrocells with individual clock, reset, preset and clock enable controls ? up to four global oe controls ? individual local oe control per i/o pin ? excellent first-time-fit tm and re t ?f ast path, speedlocking tm path, and wide-pt path ? wide input gating (36 input logic blocks) for fast counters, state machines and address decoders zero power (ispmach 4000z) and low po wer (ispmach 4000v/b/c) ?t ypical static current 10a (4032z) ?t ypical static current 1.8ma (4000c) ? 1.8v core low dynamic power broad device offering ? multiple temperature range support ? commercial: 0 to 90c junction (t j ) ? industrial: -40 to 105c junction (t j ) ? automotive: -40 to 130c junction (t j ) easy system integration ? operation with 3.3v, 2.5v or 1.8v lvcmos i/o ? operation with 3.3v (4000v), 2.5v (4000b) or 1.8v (4000c/z) supplies ? 5v tolerant i/o for lvcmos 3.3, lvttl, and pci interfaces ? hot-socketing ? open-drain capability ? input pull-up, pull-down or bus-keeper ? programmable output slew rate ? 3.3v pci compatible ? ieee 1149.1 boundary scan testable ? 3.3v/2.5v/1.8v in-system programmable (isp?) using ieee 1532 compliant interface ? i/o pins with fast setup path ta b le 1. ispmach 4000v/b/c family selection guide note: ispmach 4032z information is preliminary. ispmach 4064z/4128z information is advance. ispmach 4032v/b/c ispmach 4064v/b/c ispmach 4128v/b/c ispmach 4256v/b/c ispmach 4384v/b/c ispmach 4512v/b/c macrocells 32 64 128 256 384 512 user i/o options 30/32 30/32/64 64/92/96 64/96/128/160 128/192 128/208 t pd (ns) 2.5 2.5 2.7 3.0 3.5 3.5 t s (ns) 1.8 1.8 1.8 2.0 2.0 2.0 t co (ns) 2.2 2.2 2.7 2.7 2.7 2.7 f max (mhz) 400 400 333 322 322 322 supply voltages (v) 3.3/2.5/1.8v 3.3/2.5/1.8v 3.3/2.5/1.8v 3.3/2.5/1.8v 3.3/2.5/1.8v 3.3/2.5/1.8v pins/package 44 tqfp 48 tqfp 44 tqfp 48 tqfp 100 tqfp 100 tqfp 128 tqfp 144 tqfp 1 100 tqfp 144 tqfp 1 176 tqfp 256 fpbga 2 176 tqfp 256 fpbga 176 tqfp 256 fpbga 1. 3.3v (4000v) only. 2. 128-i/o and 160-i/o con gurations.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 2 ta b le 2. ispmach 4000z family selection guide ispmach 4000 introduction the high performance ispmach 4000 family from lattice offers a superfast cpld solution. the family is a blend of lattice?s two most popular architectures: the isplsi ? 2000 and ispmach 4a. retaining the best of both families, the ispmach 4000 architecture focuses on signi cant innovations to combine the highest performance with low power in a e xible cpld family. the ispmach 4000 combines high speed and low power with the e xibility needed for ease of design. with its robust global routing pool and output routing pool, this family delivers excellent first-time-fit, timing predictabil- ity, routing, pin-out retention and density migration. the ispmach 4000 family offers densities ranging from 32 to 512 macrocells. there are multiple density-i/o com- binations in thin quad flat pack (tqfp) and fine pitch bga (fpbga) packages ranging from 44 to 256 pins/balls. ta b le 1 shows the macrocell, package and i/o options, along with other key parameters. the ispmach 4000 family has enhanced system integration capabilities. it supports 3.3v (4000v), 2.5v (4000b) and 1.8v (4000c/z) supply voltages and 3.3v, 2.5v and 1.8v interface voltages. additionally, inputs can be safely driven up to 5.5v when an i/o bank is con gured for 3.3v operation, making this family 5v tolerant. the ispmach 4000 also offers enhanced i/o features such as slew rate control, pci compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. the ispmach 4000 family members are 3.3v/ 2.5v/1.8v in-system programmable through the ieee standard 1532 interface. ieee standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. overview the ispmach 4000 devices consist of multiple 36-input, 16-macrocell generic logic blocks (glbs) interconnected by a global routing pool (grp). output routing pools (orps) connect the glbs to the i/o blocks (iobs), which contain multiple i/o cells. this architecture is shown in figure 1. ispmach 4032zc 1 ispmach 4064zc 2 ispmach 4128zc 2 ispmach 4256zc 2 macrocells 32 64 128 256 user i/o options 32 32/64 64/96 64/96/128 t pd (ns) 3.5 4.0 4.5 5.0 t s (ns) 2.2 2.8 2.9 3.0 t co (ns) 3.0 3.3 3.9 3.9 f max (mhz) 267 250 220 200 supply voltage (v) 1.8 1.8 1.8 1.8 standby icc (a) 20 25 30 40 pins/package 48 tqfp 56 csbga 48 tqfp 56 csbga 100 tqfp 132 csbga 100 tqfp 132csbga 100 tqfp 132 csbga 176 tqfp 1. preliminary information. 2. advance information.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 3 figure 1. functional block diagram the i/os in the ispmach 4000 are split into two banks. each bank has a separate i/o power supply. inputs can support a variety of standards independent of the chip or bank power supply. outputs support the standards com- patible with the power supply provided to the bank. support for a variety of standards helps designers implement designs in mixed voltage environments. in addition, 5v tolerant inputs are speci ed within an i/o bank that is con- nected to v cco of 3.0v to 3.6v for lvcmos 3.3, lvttl and pci interfaces. ispmach 4000 architecture there are a total of two glbs in the ispmach 4032, increasing to 32 glbs in the ispmach 4512. each glb has 36 inputs. all glb inputs come from the grp and all outputs from the glb are brought back into the grp to be connected to the inputs of any other glb on the device. even if feedback signals return to the same glb, they still m ust go through the grp. this mechanism ensures that glbs communicate with each other with consistent and predictable delays. the outputs from the glb are also sent to the orp. the orp then sends them to the associ- ated i/o cells in the i/o block. generic logic block the ispmach 4000 glb consists of a programmable and array, logic allocator, 16 macrocells and a glb clock generator. macrocells are decoupled from the product terms through the logic allocator and the i/o pins are decou- pled from macrocells through the orp. figure 2 illustrates the glb. i/o block orp orp 16 16 goe0 goe1 v cc gnd tck tms tdi tdo 36 generic logic block generic logic block i/o block orp orp 16 36 generic logic block generic logic block i/o block i/o bank 0 i/o bank 1 i/o block 36 36 clk0/i clk1/i clk2/i clk3/i 16 16 global routing pool v cco0 gnd v cco1 gnd 16 16 16
lattice semiconductor ispmach 4000v/b/c/z family data sheet 4 figure 2. generic logic block and array the programmable and array consists of 36 inputs and 83 output product terms. the 36 inputs from the grp are used to form 72 lines in the and array (true and complement of the inputs). each line in the array can be con- nected to any of the 83 output product terms via a wired-and. each of the 80 logic product terms feed the logic allocator with the remaining three control product terms feeding the shared pt clock, shared pt initialization and shared pt oe. the shared pt clock and shared pt initialization signals can optionally be inverted before being f ed to the macrocells. every set of ve product terms from the 80 logic product terms forms a product term cluster starting with pt0. there is one product term cluster for every macrocell in the glb. figure 3 is a graphical representation of the and array. logic allocator 36 inputs from grp 16 macrocells to orp to grp to product term output enable sharing 1+oe 16 mc feedback signals clock generator 1+oe 1+oe 1+oe 1+oe 1+oe 1+oe clk0 clk1 clk2 clk3 1+oe and array 36 inputs, 83 product terms
lattice semiconductor ispmach 4000v/b/c/z family data sheet 5 figure 3. and array enhanced logic allocator within the logic allocator, product terms are allocated to macrocells in product term clusters. each product term cluster is associated with a macrocell. the cluster size for the ispmach 4000 family is 4+1 (total 5) product terms. the software automatically considers the availability and distribution of product term clusters as it ts the functions within a glb. the logic allocator is designed to provide three speed paths: 5-pt fast bypass path, 20-pt speed locking path and an up to 80-pt path. the availability of these three paths lets designers trade timing variability for increased performance. the enhanced logic allocator of the ispmach 4000 family consists of the following blocks: ? product term allocator ? cluster allocator ? wide steering logic figure 4 shows a macrocell slice of the logic allocator. there are 16 such slices in the glb. figure 4. macrocell slice pt0 pt1 cluster 0 pt2 pt3 pt4 in[0] in[34] in[35] note: indicates programmable fuse. pt80 pt81 pt82 shared pt clock shared pt initialization shared ptoe pt76 pt77 pt78 pt79 pt75 cluster 15 to n +1 to n -1 to n -2 from n -1 from n -4 from n +2 from n +1 5-pt f rom n -4 1-80 pts to n +4 f ast 5-pt p ath to xor (mc) cluster individual product te rm allocator cluster allocator superwide? steering logic n
lattice semiconductor ispmach 4000v/b/c/z family data sheet 6 product term allocator the product term allocator assigns product terms from a cluster to either logic or control applications as required by the design being implemented. product terms that are used as logic are steered into a 5-input or gate associ- ated with the cluster. product terms that used for control are steered either to the macrocell or i/o cell associated with the cluster. table 3 shows the available functions for each of the ve product terms in the cluster. the or gate output connects to the associated i/o cell, providing a fast path for narrow combinatorial functions, and to the logic allocator. ta b le 3. individual pt steering cluster allocator the cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions with more product terms. table 4 shows which clusters can be steered to which macrocells. used in this manner, the cluster allocator can be used to form functions of up to 20 product terms. additionally, the cluster allocator accepts inputs from the wide steering logic. using these inputs, functions up to 80 product terms can be created. ta b le 4. available clusters for each macrocell wide steering logic the wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca- tor n +4. thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions and allowing performance to be increased through a single glb implementation. table 5 shows the product term chains. product term logic control pt n logic pt single pt for xor/or pt n +1 logic pt individual clock (pt clock) pt n +2 logic pt individual initialization or individual clock enable (pt initialization/ce) pt n +3 logic pt individual initialization (pt initialization) pt n +4 logic pt individual oe (ptoe) macrocell available clusters m0 ? c0 c 1c2 m1 c0 c1 c2 c3 m2 c1 c2 c3 c4 m3 c2 c3 c4 c5 m4 c3 c4 c5 c6 m5 c4 c5 c6 c7 m6 c5 c6 c7 c8 m7 c6 c7 c8 c9 m8 c7 c8 c9 c10 m9 c8 c9 c10 c11 m10 c9 c10 c11 c12 m11 c10 c11 c12 c13 m12 c11 c12 c13 c14 m13 c12 c13 c14 c15 m14 c13 c14 c15 ? m15 c14 c15 ? ?
lattice semiconductor ispmach 4000v/b/c/z family data sheet 7 ta b le 5. product term expansion capability every time the super cluster allocator is used, there is an incremental delay of t exp . when the super cluster alloca- tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus- ter is steered to m (n+4), then m (n) is ground). macrocell the 16 macrocells in the glb are driven by the 16 outputs from the logic allocator. each macrocell contains a pro- gr ammable xor gate, a programmable register/latch, along with routing for the logic and control functions. figure 5 shows a graphical representation of the macrocell. the macrocells feed the orp and grp. a direct input from the i/o cell allows designers to use the macrocell to construct high-speed input registers. a programmable delay in this path allows designers to choose between the fastest possible set-up time and zero hold time. figure 5. macrocell enhanced clock multiplexer the clock input to the ip- op can select any of the four block clocks along with the shared pt clock, and true and complement forms of the optional individual term clock. an 8:1 multiplexer structure is used to select the clock. the eight sources for the clock multiplexer are as follows: ? block clk0 ? block clk1 expansion chains macrocells associated with expansion chain (with wrap around) max pt/ macrocell chain-0 m0 m4 m8 m12 m0 75 chain-1 m1 m5 m9 m13 m1 80 chain-2 m2 m6 m10 m14 m2 75 chain-3 m3 m7 m11 m15 m3 70 single pt block clk0 block clk1 block clk2 block clk3 pt clock (optional) shared pt clock ce d/t/l q rp shared pt initialization pt initialization/ce (optional) pt initialization (optional) from logic allocator power-up initialization to orp to grp from i/o cell delay
lattice semiconductor ispmach 4000v/b/c/z family data sheet 8 ? block clk2 ? block clk3 ? pt clock ? pt clock inverted ? shared pt clock ? ground clock enable multiplexer each macrocell has a 4:1 clock enable multiplexer. this allows the clock enable signal to be selected from the fol- lowing four sources: ? pt initialization/ce ? pt initialization/ce inverted ? shared pt clock ? logic high initialization control the ispmach 4000 family architecture accommodates both block-level and macrocell-level set and reset capability. there is one block-level initialization term that is distributed to all macrocell registers in a glb. at the macrocell level, two product terms can be ?stolen? from the cluster associated with a macrocell to be used for set/reset func- tionality. a reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing e xibility. note that the reset/preset swapping selection feature affects power-up reset as well. all ip- ops power up to a known state for predictable system initialization. if a macrocell is con gured to set on a signal from the block-level initialization, then that macrocell will be set during device power-up. if a macrocell is con gured to reset on a signal from the block-level initialization or is not con gured for set/reset, then that macrocell will reset on power- up. to guarantee initialization values, the v cc r ise must be monotonic, and the clock must be inactive until the reset delay time has elapsed. glb clock generator each ispmach 4000 device has up to four clock pins that are also routed to the grp to be used as inputs. these pins drive a clock generator in each glb, as shown in figure 6. the clock generator provides four clock signals that can be used anywhere in the glb. these four glb clock signals can consist of a number of combinations of the true and complement edges of the global clock signals. figure 6. glb clock generator clk0 clk1 clk2 clk3 block clk0 block clk1 block clk2 block clk3
lattice semiconductor ispmach 4000v/b/c/z family data sheet 9 output routing pool (orp) the output routing pool allows macrocell outputs to be connected to any of several i/o cells within an i/o block. this provides greater e xibility in determining the pinout and allows design changes to occur without affecting the pinout. the output routing pool also provides a parallel capability for routing macrocell-level oe product terms. this allows the oe product term to follow the macrocell output as it is switched between i/o cells. additionally, the out- put routing pool allows the macrocell output or true and complement forms of the 5-pt bypass signal to bypass the output routing multipliers and feed the i/o cell directly. the enhanced orp of the ispmach 4000 family consists of the following elements: ? output routing multiplexers ? oe routing multiplexers ? output routing pool bypass multiplexers figure 7 shows the structure of the orp from the i/o cell perspective. this is referred to as an orp slice. each orp has as many orp slices as there are i/o cells in the corresponding i/o block. figure 7. orp slice output routing multiplexers the details of connections between the macrocells and the i/o cells vary across devices and within a device dependent on the maximum number of i/os available. tables 5-9 provide the connection details. ta b le 6. orp combinations for i/o blocks with 8 i/os i/o cell available macrocells i/o 0 m0, m1, m2, m3, m4, m5, m6, m7 i/o 1 m2, m3, m4, m5, m6, m7, m8, m9 i/o 2 m4, m5, m6, m7, m8, m9, m10, m11 i/o 3 m6, m7, m8, m9, m10, m11, m12, m13 i/o 4 m8, m9, m10, m11, m12, m13, m14, m15 i/o 5 m10, m11, m12, m13, m14, m15, m0, m1 i/o 6 m12, m13, m14, m15, m0, m1, m2, m3 i/o 7 m14, m15, m0, m1, m2, m3, m4, m5 out p ut routin g multi p lexer oe routing multiplexer orp bypass multiplexer f rom macrocell f rom ptoe to i/o cell to i/o cell output oe 5-pt fast path
lattice semiconductor ispmach 4000v/b/c/z family data sheet 10 ta b le 7. orp combinations for i/o blocks with 16 i/os ta b le 8. orp combinations for i/o blocks with 4 i/os ta b le 9. orp combinations for i/o blocks with 10 i/os i/o cell available macrocells i/o 0 m0, m1, m2, m3, m4, m5, m6, m7 i/o 1 m1, m2, m3, m4, m5, m6, m7, m8 i/o 2 m2, m3, m4, m5, m6, m7, m8, m9 i/o 3 m3, m4, m5, m6, m7, m8, m9, m10 i/o 4 m4, m5, m6, m7, m8, m9, m10, m11 i/o 5 m5, m6, m7, m8, m9, m10, m11, m12 i/o 6 m6, m7, m8, m9, m10, m11, m12, m13 i/o 7 m7, m8, m9, m10, m11, m12, m13, m14 i/o 8 m8, m9, m10, m11, m12, m13, m14, m15 i/o 9 m9, m10, m11, m12, m13, m14, m15, m0 i/o 10 m10, m11, m12, m13, m14, m15, m0, m1 i/o 11 m11, m12, m13, m14, m15, m0, m1, m2 i/o 12 m12, m13, m14, m15, m0, m1, m2, m3 i/o 13 m13, m14, m15, m0, m1, m2, m3, m4 i/o 14 m14, m15, m0, m1, m2, m3, m4, m5 i/o 15 m15, m0, m1, m2, m3, m4, m5, m6 i/o cell available macrocells i/o 0 m0, m1, m2, m3, m4, m5, m6, m7 i/o 1 m4, m5, m6, m7, m8, m9, m10, m11 i/o 2 m8, m9, m10, m11, m12, m13, m14, m15 i/o 3 m12, m13, m14, m15, m0, m1, m2, m3 i/o cell available macrocells i/o 0 m0, m1, m2, m3, m4, m5, m6, m7 i/o 1 m2, m3, m4, m5, m6, m7, m8, m9 i/o 2 m4, m5, m6, m7, m8, m9, m10, m11 i/o 3 m6, m7, m8, m9, m10, m11, m12, m13 i/o 4 m8, m9, m10, m11, m12, m13, m14, m15 i/o 5 m10, m11, m12, m13, m14, m15, m0, m1 i/o 6 m12, m13, m14, m15, m0, m1, m2, m3 i/o 7 m14, m15, m0, m1, m2, m3, m4, m5 i/o 8 m2, m3, m4, m5, m6, m7, m8, m9 i/o 9 m10, m11, m12, m13, m14, m15, m0, m1
lattice semiconductor ispmach 4000v/b/c/z family data sheet 11 ta b le 10. orp combinations for i/o blocks with 12 i/os orp bypass and fast output multiplexers the orp bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-pt fast path to bypass the orp and be connected directly to the pin with either the regular output or the inverted output. this multiplexer also allows the register output to bypass the orp to achieve faster t co . output enable routing multiplexers the oe routing pool provides the corresponding local output enable (oe) product term to the i/o cell. i/o cell the i/o cell contains the following programmable elements: output buffer, input buffer, oe multiplexer and bus maintenance circuitry. figure 8 details the i/o cell. figure 8. i/o cell each output supports a variety of output standards dependent on the v cco supplied to its i/o bank. outputs can also be con gured for open drain operation. each input can be programmed to support a variety of standards, inde- pendent of the v cco supplied to its i/o bank. the i/o standards supported are: i/o cell available macrocells i/o 0 m0, m1, m2, m3, m4, m5, m6, m7 i/o 1 m1, m2, m3, m4, m5, m6, m7, m8 i/o 2 m2, m3, m4, m5, m6, m7, m8, m9 i/o 3 m4, m5, m6, m7, m8, m9, m10, m11 i/o 4 m5, m6, m7, m8, m9, m10, m11, m12 i/o 5 m6, m7, m8, m9, m10, m11, m12, m13 i/o 6 m8, m9, m10, m11, m12, m13, m14, m15 i/o 7 m9, m10, m11, m12, m13, m14, m15, m0 i/o 8 m10, m11, m12, m13, m14, m15, m0, m1 i/o 9 m12, m13, m14, m15, m0, m1, m2, m3 i/o 10 m13, m14, m15, m0, m1, m2, m3, m4 i/o 11 m14, m15, m0, m1, m2, m3, m4, m5 goe 0 f rom orp *global fuses f rom orp to macrocell to grp goe 1 goe 2 goe 3 vcc v cco v cco ** *
lattice semiconductor ispmach 4000v/b/c/z family data sheet 12 ?l vttl ? lvcmos 1.8 ?l vcmos 3.3 ? 3.3v pci compatible ?l vcmos 2.5 all of the i/os and dedicated inputs have the capability to provide a bus-keeper latch, pull-up resistor or pull-down resistor. a fourth option is to provide none of these. the selection is done on a global basis. the default in both hardware and software is such that when the device is erased or if the user does not specify, the input structure is con gured to be a pull-up resistor. each ispmach 4000 device i/o has an individually programmable output slew rate control bit. each output can be individually con gured for the higher speed transition (~3v/ns) or for the lower noise transition (~1v/ns). for high- speed designs with long, unterminated traces, the slow-slew rate will introduce fewer re ections, less noise and k eep ground bounce to a minimum. for designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. the slew rate is adjusted independent of power. global oe generation most ispmach 4000 family devices have a 4-bit wide global oe bus, except the ispmach 4032 device that has a 2-bit wide global oe bus. this bus is derived from a 4-bit internal global oe pt bus and two dual purpose i/o or goe pins. each signal that drives the bus can optionally be inverted. each glb has a block-level oe pt that connects to all bits of the global oe pt bus with four fuses. hence, for a 256-macrocell device (with 16 blocks), each line of the bus is driven from 16 oe product terms. figures 9 and 10 show a graphical representation of the global oe generation. figure 9. global oe generation for all devices except ispmach 4032 shared ptoe (block 0) shared ptoe (block n) global fuses goe (0:3) to i/o cells internal global oe pt bus (4 lines) 4-bit global oe bus global oe fuse connection hard wired
lattice semiconductor ispmach 4000v/b/c/z family data sheet 13 figure 10. global oe generation for ispmach 4032 zero power/low power and power management the ispmach 4000 family is designed with high speed low power design techniques to offer both high speed and low power. with an advanced e 2 low power cell and non sense-ampli er design approach (full cmos logic approach), the ispmach 4000 family offers superfast pin-to-pin speeds, while simultaneously delivering low standby power without needing any ?turbo bits? or other power management schemes associated with a traditional sense-ampli er approach. the zero power ispmach 4000z is based on the 1.8v ispmach 4000c family. with innovative circuit design changes, the ispmach 4000z family is able to achieve the industry?s ?lowest static power?. ieee 1149.1-compliant boundary scan testability all ispmach 4000 devices have boundary scan cells and are compliant to the ieee 1149.1 standard. this allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic notes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for veri cation. in addition, these devices can be linked into a board-level serial scan path for more board-level testing. the test access port operates with an lvcmos interface that corresponds to the power supply voltage. i/o quick con guration to f acilitate the most ef cient board test, the physical nature of the i/o cells must be set before running any continu- ity tests. as these tests are fast, by nature, the overhead and time that is required for con guration of the i/os? physical nature should be minimal so that board test time is minimized. the ispmach 4000 family of devices allows this by offering the user the ability to quickly con gure the physical nature of the i/o cells. this quick con guration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. lattice's ispvm? system programming software can either perform the quick con guration through the pc parallel port, or can generate the ate or test vectors necessary for a third-party test system. shared ptoe (block 0) shared ptoe (block 1) global fuses goe (3:0) to i/o cells internal global oe pt bus (2 lines) 4-bit global oe bus global oe fuse connection hard wired
lattice semiconductor ispmach 4000v/b/c/z family data sheet 14 ieee 1532-compliant in-system programming programming devices in-system provides a number of signi cant bene ts including: rapid prototyping, lower inven- tory levels, higher quality and the ability to make in- eld modi cations. all ispmach 4000 devices provide in-sys- tem programming (isp?) capability through the boundary scan test access port. this capability has been implemented in a manner that ensures that the port remains complaint to the ieee 1149.1 standard. by using ieee 1149.1 as the communication interface through which isp is achieved, users get the bene t of a standard, well- de ned interface. all ispmach 4000 devices are also compliant with the ieee 1532 standard. the ispmach 4000 devices can be programmed across the commercial temperature and voltage range. the pc- based lattice software facilitates in-system programming of ispmach 4000 devices. the software takes the jedec le output produced by the design implementation software, along with information about the scan chain, and creates a set of vectors used to drive the scan chain. the software can use these vectors to drive a scan chain via the parallel port of a pc. alternatively, the software can output les in formats understood by common auto- mated test equipment. this equipment can then be used to program ispmach 4000 devices during the testing of a circuit board. security bit a programmable security bit is provided on the ispmach 4000 devices as a deterrent to unauthorized copying of the array con guration patterns. once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. programming and veri cation are also defeated by the security bit. the bit can only be reset by erasing the entire device. hot socketing the ispmach 4000 devices are well-suited for applications that require hot socketing capability. hot socketing a device requires that the device, during power-up and down, can tolerate active signals on the i/os and inputs with- out being damaged. additionally, it requires that the effects of i/o pin loading be minimal on active signals. the ispmach 4000 devices provide this capability for input voltages in the range 0v to 3.0v. density migration the ispmach 4000 family has been designed to ensure that different density devices in the same package have the same pin-out. furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. in many cases, it is possible to shift a lower utilization design tar- geted for a high density device to a lower density device. however, the exact details of the nal resource utilization will impact the likely success in each case.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 15 absolute maximum ratings 1, 2, 3 ispmach 4000c/z ispmach 4000b ispmach 4000v (1.8v) (2.5v) (3.3v) supply voltage (v cc ). . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5v . . . . . . . . . .-0.5 to 5.5v . . . . . . . . . . . -0.5 to 5.5v output supply voltage (v cco ). . . . . . . . . . . . . . . -0.5 to 4.5v . . . . . . . . . .-0.5 to 4.5v . . . . . . . . . . . -0.5 to 4.5v input or i/o tristate voltage applied 4, 5 . . . . . . . . . -0.5 to 5.5v . . . . . . . . . .-0.5 to 5.5v . . . . . . . . . . . -0.5 to 5.5v storage temperature . . . . . . . . . . . . . . . . . . . . . . -65 to 150 c. . . . . . . . . -65 to 150 c . . . . . . . . . .-65 to 150 c j unction temperature (t j ) with power applied . . . -55 to 150 c. . . . . . . . . -55 to 150 c . . . . . . . . . .-55 to 150 c 1. stress above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci cation is not implied. 2. compliance with lattice thermal management document is required. 3. all voltages referenced to gnd. 4. undershoot of -2v and overshoot of (v ih (max) + 2v), up to a total pin voltage of 6.0v, is permitted for a duration of < 20ns. 5. maximum of 64 i/os per device with vin > 3.6v is allowed. recommended operating conditions erase reprogram speci cations hot socketing characteristics 1,2,3 symbol parameter min. max. units v cc supply voltage for 1.8v devices ispmach 4000c 1.65 1.95 v ispmach 4000z 1.7 1.9 v supply voltage for 2.5v devices 2.3 2.7 v supply voltage for 3.3v devices 3.0 3.6 v t j j unction temperature (commercial) 0 90 c j unction temperature (industrial) -40 105 c j unction temperature (automotive) -40 130 c p arameter min. max. units erase/reprogram cycle 1,000 ? cycles note: valid over commercial temperature range. symbol parameter condition min. typ. max. units i dk input or i/o leakage current 0 v in 3.0v, tj = 105c ? 30 150 a 0 v in 3.0v, tj = 130c ? 30 200 a 1. insensitive to sequence of v cc or v cco. however, assumes monotonic rise/fall rates for v cc and v cco, provided (v in - v cco ) 3.0v. 2. 0 < v cc < v cc (max), 0 < v cco < v cco (max). 3. i dk is additive to i pu , i pd or i bh . device defaults to pull-up until fuse circuitry is active.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 16 i/o recommended operating conditions dc electrical characteristics over recommended operating conditions standard v cco (v) 1 min. max. l vttl 3.0 3.6 l vcmos 3.3 3.0 3.6 extended lvcmos 3.3 2 2.7 3.6 l vcmos 2.5 2.3 2.7 l vcmos 1.8 1.65 1.95 pci 3.3 3.0 3.6 1. typical values for v cco are the average of the min. and max. values. 2. ispmach 4000z only. symbol parameter condition min. typ. max. units i il , i ih 1 input leakage current 0 < v in 3.6v, t j = 105c ? ? 10 a 0 < v in 3.6v, t j = 130c ? ? 15 a i ih 2 input high leakage current 3.6v < v in 5.5v, t j = 105c 3.0v v cco 3.6v ??20 a 3.6v < v in 5.5v, t j = 130c 3.0v v cco 3.6v ??50 a i pu i/o weak pull-up resistor current 0 v in 0.7v cco -30 ? -150 a i pd i/o weak pull-down resistor current v il (max) v in v ih (min) 30 ? 150 a i bhls bus hold low sustaining current v in = v il (max) 30 ? ? a i bhhs bus hold high sustaining current v in = 0.7 v cco -30 ? ? a i bhlo bus hold low overdrive current 0v v in v bht ?? 150 a i bhho bus hold high overdrive current v bht v in v cco ?? -150 a v bht bus hold trip points ? v cco * 0.35 ? v cco * 0.65 v c 1 i/o capacitance 3 v cco = 3.3v, 2.5v, 1.8v ? 8 ? pf v cc = 1.8v, v io = 0 to v ih (max) ? ? c 2 clock capacitance 3 v cco = 3.3v, 2.5v, 1.8v ? 6 ? pf v cc = 1.8v, v io = 0 to v ih (max) ? ? c 3 global input capacitance 3 v cco = 3.3v, 2.5v, 1.8v ? 6 ? pf v cc = 1.8v, v io = 0 to v ih (max) ? ? 1. input or i/o leakage current is measured with the pin con gured as an input or as an i/o with the output driver tristated. it is not measured with the output driver active. bus maintenance circuits are disabled. 2. 5v tolerant inputs and i/o should only be placed in banks where 3.0v v cco 3.6v. 3. t a = 25c, f = 1.0mhz
lattice semiconductor ispmach 4000v/b/c/z family data sheet 17 supply current, ispmach 4000v/b/c over recommended operating conditions symbol parameter condition min. typ. max. units ispmach 4032v/b/c icc 1,2,3 operating power supply current vcc = 3.3v ? 11.8 ? ma vcc = 2.5v ? 11.8 ? ma vcc = 1.8v ? 1.8 ? ma icc 4 standby power supply current vcc = 3.3v ? 11.3 ? ma vcc = 2.5v ? 11.3 ? ma vcc = 1.8v ? 1.3 ? ma ispmach 4064v/b/c icc 1,2,3 operating power supply current vcc = 3.3v ? 12 ? ma vcc = 2.5v ? 12 ? ma vcc = 1.8v ? 2 ? ma icc 5 standby power supply current vcc = 3.3v ? 11.5 ? ma vcc = 2.5v ? 11.5 ? ma vcc = 1.8v ? 1.5 ? ma ispmach 4128v/b/c icc 1,2,3 operating power supply current vcc = 3.3v ? 12 ? ma vcc = 2.5v ? 12 ? ma vcc = 1.8v ? 2 ? ma icc 4 standby power supply current vcc = 3.3v ? 11.5 ? ma vcc = 2.5v ? 11.5 ? ma vcc = 1.8v ? 1.5 ? ma ispmach 4256v/b/c i cc 1,2,3 operating power supply current vcc = 3.3v ? 12.5 ? ma vcc = 2.5v ? 12.5 ? ma vcc = 1.8v ? 2.5 ? ma i cc 4 standby power supply current vcc = 3.3v ? 12 ? ma vcc = 2.5v ? 12 ? ma vcc = 1.8v ? 2 ? ma ispmach 4384v/b/c i cc 1,2,3 operating power supply current vcc = 3.3v ? 13.5 ? ma vcc = 2.5v ? 13.5 ? ma vcc = 1.8v ? 3.5 ? ma i cc 4 standby power supply current vcc = 3.3v ? 12.5 ? ma vcc = 2.5v ? 12.5 ? ma vcc = 1.8v ? 2.5 ? ma ispmach 4512v/b/c i cc 1,2,3 operating power supply current vcc = 3.3v ? 14 ? ma vcc = 2.5v ? 14 ? ma vcc = 1.8v ? 4 ? ma
lattice semiconductor ispmach 4000v/b/c/z family data sheet 18 i cc 4 standby power supply current vcc = 3.3v ? 13 ? ma vcc = 2.5v ? 13 ? ma vcc = 1.8v ? 3 ? ma 1. t a = 25c, frequency = 1.0 mhz. 2. device con gured with 16-bit counters. 3. i cc varies with speci c device con guration and operating frequency. 4. t a = 25c supply current, ispmach 4000z over recommended operating conditions symbol parameter condition min. typ. max. units ispmach 4032zc 1 icc 3, 4, 5, 7 operating power supply current vcc = 1.8v, t a = 25c ? 50 ? a vcc = 1.9v, t a = 70c ? 58 ? a vcc = 1.9v, t a = 85c ? 60 ? a vcc = 1.9v, t a = 125c ? 70 ? a icc 6, 7 standby power supply current vcc = 1.8v, t a = 25c ? 10 ? a vcc = 1.9v, t a = 70c ? 16 20 a vcc = 1.9v, t a = 85c ? 18 22 a vcc = 1.9v, t a = 125c ? 22 ? a ispmach 4064zc 2 icc 3, 4, 5, 7 operating power supply current vcc = 1.8v, t a = 25c ? ? a vcc = 1.9v, t a = 70c ? ? a vcc = 1.9v, t a = 85c ? ? a vcc = 1.9v, t a = 125c ? ? a icc 6, 7 standby power supply current vcc = 1.8v, t a = 25c ? ? a vcc = 1.9v, t a = 70c ? ? a vcc = 1.9v, t a = 85c ? ? a vcc = 1.9v, t a = 125c ? ? a ispmach 4128zc 2 icc 3, 4, 5, 7 operating power supply current vcc = 1.8v, t a = 25c ? ? a vcc = 1.9v, t a = 70c ? ? a vcc = 1.9v, t a = 85c ? ? a vcc = 1.9v, t a = 125c ? ? a icc 6, 7 standby power supply current vcc = 1.8v, t a = 25c ? ? a vcc = 1.9v, t a = 70c ? ? a vcc = 1.9v, t a = 85c ? ? a vcc = 1.9v, t a = 125c ? ? a supply current, ispmach 4000v/b/c (cont.) over recommended operating conditions symbol parameter condition min. typ. max. units
lattice semiconductor ispmach 4000v/b/c/z family data sheet 19 ispmach 4256zc 2 icc 3, 4, 5, 7 operating power supply current vcc = 1.8v, t a = 25c ? ? a vcc = 1.9v, t a = 70c ? ? a vcc = 1.9v, t a = 85c ? ? a vcc = 1.9v, t a = 125c ? ? a icc 6, 7 standby power supply current vcc = 1.8v, t a = 25c ? ? a vcc = 1.9v, t a = 70c ? ? a vcc = 1.9v, t a = 85c ? ? a vcc = 1.9v, t a = 125c ? ? a 1. preliminary information. 2. advance information. 3. t a = 25c, frequency = 1.0 mhz. 4. device con gured with 16-bit counters. 5. i cc varies with speci c device con guration and operating frequency. 6. v cco = 3.6v, v in = 0v or v cco, bus maintenance turned off. v in above v cco will add transient current above the speci ed standby i cc . 7. includes v cco current without output loading. supply current, ispmach 4000z (cont.) over recommended operating conditions symbol parameter condition min. typ. max. units
lattice semiconductor ispmach 4000v/b/c/z family data sheet 20 i/o dc electrical characteristics over recommended operating conditions standard v il v ih v ol max (v) v oh min (v) i ol 1 (ma) i oh 1 (ma) min (v) max (v) min (v) max (v) l vttl -0.3 0.80 2.0 5.5 0.40 v cco - 0.40 8.0 -4.0 0.20 v cco - 0.20 0.1 -0.1 l vcmos 3.3 -0.3 0.80 2.0 5.5 0.40 v cco - 0.40 8.0 -4.0 0.20 v cco - 0.20 0.1 -0.1 l vcmos 2.5 -0.3 0.70 1.70 3.6 0.40 v cco - 0.40 8.0 -4.0 0.20 v cco - 0.20 0.1 -0.1 l vcmos 1.8 (4000v/b) -0.3 0.63 1.17 3.6 0.40 v cco - 0.45 2.0 -2.0 0.20 v cco - 0.20 0.1 -0.1 l vcmos 1.8 (4000c/z) -0.3 0.35 * v cc 0.65 * v cc 3.6 0.40 v cco - 0.45 2.0 -2.0 0.20 v cco - 0.20 0.1 -0.1 pci 3.3 (4000v/b) -0.3 1.08 1.5 5.5 0.1 v cco 0.9 v cco 1.5 -0.5 pci 3.3 (4000c/z) -0.3 0.3 * 3.3 * (v cc / 1.8) 0.5 * 3.3 * (v cc / 1.8) 5.5 0.1 v cco 0.9 v cco 1.5 -0.5 1. the average dc current drawn by i/os between adjacent bank gnd connections, or between the last gnd in an i/o bank and the e nd of the i/o bank, as shown in the logic signals connection table, shall not exceed n *8ma. where n is the number of i/os between bank gnd connections or between the last gnd in a bank and the end of a bank.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 21 v o output voltage (v) typical i/o output current (ma) 3.3v v cco v o output voltage (v) 0 0 0 20 40 60 80 100 10 20 30 40 50 60 0 10 20 30 40 50 60 70 2.0 1.5 1.0 0.5 0 2.0 2.5 3.0 3.5 1.5 1.0 0.5 0 2.0 2.5 1.5 1.0 0.5 typical i/o output current (ma) 1.8v v cco v o output voltage (v) i oh typical i/o output current (ma) 2.5v v cco i ol i oh i ol i oh i ol
lattice semiconductor ispmach 4000v/b/c/z family data sheet 22 ispmach 4000v/b/c external switching characteristics over recommended operating conditions p arameter description 1, 2, 3 -25 -27 -3 -35 units min. max. min. max. min. max. min. max. t pd 5-pt bypass combinatorial propagation delay ?2.5?2.7? 3.0 ? 3.5 ns t pd_mc 20-pt combinatorial propagation delay through macrocell ?3.2?3.5? 3.8 ? 4.2 ns t s glb register setup time before clock 1.8 ? 1.8 ? 2.0 ? 2.0 ? ns t st glb register setup time before clock with t-type register 2.0 ? 2.0 ? 2.2 ? 2.2 ? ns t sir glb register setup time before clock, input register path 0.7 ? 1.0 ? 1.0 ? 1.0 ? ns t sirz glb register setup time before clock with zero hold 1.7 ? 2.0 ? 2.0 ? 2.0 ? ns t h glb register hold time after clock 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t ht glb register hold time after clock with t -type register 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t hir glb register hold time after clock, input register path 0.9 ? 1.0 ? 1.0 ? 1.0 ? ns t hirz glb register hold time after clock, input register path with zero hold 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t co glb register clock-to-output delay ? 2.2 ? 2.7 ? 2.7 ? 2.7 ns t r external reset pin to output delay ? 3.5 ? 4.0 ? 4.4 ? 4.5 ns t rw external reset pulse duration 1.5 ? 1.5 ? 1.5 ? 1.5 - ns t ptoe/dis input to output local product term output enable/disable ?4.0?4.5? 5.0 ? 5.5 ns t gptoe/dis input to output global product term output enable/disable ?5.0?6.5? 8.0 ? 8.0 ns t goe/dis global oe input to output enable/disable ? 3.0 ? 3.5 ? 4.0 ? 4.5 ns t cw global clock width, high or low 1.1 ? 1.3 ? 1.3 ? 1.3 ? ns t gw global gate width low (for low transparent) or high (for high transparent) 1.1 ? 1.3 ? 1.3 ? 1.3 ? ns t wir input register clock width, high or low 1.1 ? 1.3 ? 1.3 ? 1.3 ? ns f max 4 clock frequency with internal feedback 400 ? 333 ? 322 ? 322 ? mhz f max (ext.) clock frequency with external feedback, [1/ (t s + t co )] 250 ? 222 ? 212 ? 212 ? mhz 1. timing numbers are based on default lvcmos 1.8 i/o buffers. use timing adjusters provided to calculate other standards. timing v.3.1 2. measured using standard switching circuit, assuming grp loading of 1 and 1 output switching. 3. pulse widths and clock widths less than minimum will cause unknown behavior. 4. standard 16-bit counter using grp feedback.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 23 ispmach 4000v/b/c external switching characteristics (cont.) over recommended operating conditions p arameter description 1, 2, 3 -5 -75 -10 units min. max. min. max. min. max. t pd 5-pt bypass combinatorial propagation delay ? 5.0 ? 7.5 ? 10.0 ns t pd_mc 20-pt combinatorial propagation delay through macrocell ? 5.5 ? 8.0 ? 10.5 ns t s glb register setup time before clock 3.0 ? 4.5 ? 5.5 ? ns t st glb register setup time before clock with t-type register 3.2 ? 4.7 ? 5.5 ? ns t sir glb register setup time before clock, input register path 1.2 ? 1.7 ? 1.7 ? ns t sirz glb register setup time before clock with zero hold 2.2 ? 2.7 ? 2.7 ? ns t h glb register hold time after clock 0.0 ? 0.0 ? 0.0 ? ns t ht glb register hold time after clock with t-type register 0.0 ? 0.0 ? 0.0 ? ns t hir glb register hold time after clock, input register path 1.0 ? 1.0 ? 1.0 ? ns t hirz glb register hold time after clock, input register path with z ero hold 0.0 ? 0.0 ? 0.0 ? ns t co glb register clock-to-output delay ? 3.40 ? 4.5 ? 6.0 ns t r external reset pin to output delay ? 6.30 ? 9.0 ? 10.5 ns t rw external reset pulse duration 2.0 ? 4.0 ? 4.0 ? ns t ptoe/dis input to output local product term output enable/disable ? 7.00 ? 9.0 ? 10.5 ns t gptoe/dis input to output global product term output enable/disable ? 9.00 ? 10.3 ? 12.0 ns t goe/dis global oe input to output enable/disable ? 5.00 ? 7.0 ? 8.0 ns t cw global clock width, high or low 2.2 ? 3.3 ? 4.0 ? ns t gw global gate width low (for low transparent) or high (for high transparent) 2.2 ? 3.3 ? 4.0 ? ns t wir input register clock width, high or low 2.2 ? 3.3 ? 4.0 ? ns f max 4 clock frequency with internal feedback 227 ? 168 ? 125 ? mhz f max (ext.) clock frequency with external feedback, [1/ (t s + t co )] 156 ? 111 ? 86 ? mhz 1. timing numbers are based on default lvcmos 1.8 i/o buffers. use timing adjusters provided to calculate other standards. timing v.3.1 2. measured using standard switching circuit, assuming grp loading of 1 and 1 output switching. 3. pulse widths and clock widths less than minimum will cause unknown behavior. 4. standard 16-bit counter using grp feedback.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 24 ispmach 4032z external switching characteristics 1 over recommended operating conditions p arameter description 2, 3, 4 -35 -5 -75 units min. max. min. max. min. max. t pd 5-pt bypass combinatorial propagation delay ? 3.5 ? 5.0 ? 7.5 ns t pd_mc 20-pt combinatorial propagation delay through macrocell ? 4.4 ? 5.5 ? 8.0 ns t s glb register setup time before clock 2.2 ? 3.0 ? 4.5 ? ns t st glb register setup time before clock with t-type register 2.5 ? 3.2 ? 4.7 ? ns t sir glb register setup time before clock, input register path 1.0 ? 1.2 ? 1.7 ? ns t sirz glb register setup time before clock with zeto hold 2.0 ? 2.2 ? 2.7 ? ns t h glb register hold time after clock 0.0 ? 0.0 ? 0.0 ? ns t ht glb register hold time after clock with t-type register 0.0 ? 0.0 ? 0.0 ? ns t hir glb register hold time after clock, input register path 1.0 ? 1.0 ? 1.0 ? ns t hirz glb register hold time after clock, input register path with z ero hold 0.0 ? 0.0 ? 0.0 ? ns t co glb register clock-to-output delay ? 3.0 ? 3.4 ? 4.5 ns t r external reset pin to output delay ? 5.0 ? 6.3 ? 9.0 ns t rw external reset pulse duration 1.5 ? 2.0 ? 4.0 ? ns t ptoe/dis input to output local product term output enable/disable ? 7.0 ? 8.0 ? 9.0 ns t gptoe/dis input to output global product term output enable/disable ? 6.5 ? 8.0 ? 9.0 ns t goe/dis global oe input to output enable/disable ? 4.5 ? 5.0 ? 7.0 ns t cw global clock width, high or low 1.0 ? 2.2 ? 3.3 ? ns t gw global gate width low (for low transparent) or high (for high transparent) 1.0 ? 2.2 ? 3.3 ? ns t wir input register clock width, high or low 1.0 ? 2.2 ? 3.3 ? ns f max 5 clock frequency with internal feedback 267 ? 200 ? 150 ? mhz t max (ext.) clock frequency with external feedback, [1/(ts + tco)] 192 ? 156 ? 111 ? mhz timing v.1.2 1. preliminary information. 2. timing numbers are based on default lvcmos 1.8 i/o buffers. use timing adjusters provided to calculate other standards. 3. measured using standard switching grp loading of 1 and 1 output switching. 4. pulse widths and clock widths less than minimum will cause unknown behavior. 5. standard 16-bit counter using grp feedback.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 25 timing model the task of determining the timing through the ispmach 4000 family, like any cpld, is relatively simple. the timing model provided in figure 11 shows the speci c delay paths. once the implementation of a given function is deter- mined either conceptually or from the software report le, the delay path of the function can easily be determined from the timing model. the lattice design tools report the timing delays based on the same timing model for a par- ticular design. note that the internal timing parameters are given for reference only, and are not tested. the exter- nal timing parameters are tested and guaranteed for every device. for more information on the timing model and usage, please refer to technical note tn1004: ispmach 4000 timing model design and usage guidelines. figure 11. ispmach 4000 timing model data mc reg. c.e. s/r q sclk in oe in/out delays in/out delays control delays register/latch delays routing/glb delays out note: italicized items are optional delay adders. t fbk feedback from feedback t buf t pdb t mcell t ptclk t bclk t ptsr t bsr t gptoe t ptoe t exp t route t bla t inreg t indio t in t ioi t gclk_in t ioi t goe t ioi t pdi t ioo t orp t en t dis
lattice semiconductor ispmach 4000v/b/c/z family data sheet 26 ispmach 4000v/b/c internal timing parameters over recommended operating conditions p arameter description -2.5 -2.7 -3 -3.5 units in/out delays t in input buffer delay ? 0.60 ? 0.60 ? 0.70 ? 0.70 ns t goe global oe pin delay ? 2.04 ? 2.54 ? 3.04 ? 3.54 ns t gclk_in global clock input buffer delay ? 0.78 ? 1.28 ? 1.28 ? 1.28 ns t buf delay through output buffer ? 0.85 ? 0.85 ? 0.85 ? 0.85 ns t en output enable time ? 0.96 ? 0.96 ? 0.96 ? 0.96 ns t dis output disable time ? 0.96 ? 0.96 ? 0.96 ? 0.96 ns routing/glb delays t r oute delay through grp ? 0.61 ? 0.81 ? 1.01 ? 1.01 ns t mcell macrocell delay ? 0.45 ? 0.55 ? 0.55 ? 0.65 ns t inreg input buffer to macrocell register delay ? 0.11 ? 0.31 ? 0.31 ? 0.31 ns t fbk internal feedback delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t pdb 5-pt bypass propagation delay ? 0.44 ? 0.44 ? 0.44 ? 0.94 ns t pdi macrocell propagation delay ? 0.64 ? 0.64 ? 0.64 ? 0.94 ns register/latch delays t s d-register setup time (global clock) 0.92 ? 1.12 ? 1.02 ? 0.92 ? ns t s_pt d-register setup time (product term clock) 1.42 ? 1.32 ? 1.32 ? 1.32 ? ns t st t -register setup time (global clock) 1.12 ? 1.32 ? 1.22 ? 1.12 ? ns t st_pt t -register setup time (product term clock) 1.42 ? 1.32 ? 1.32 ? 1.32 ? ns t h d-register hold time 0.88 ? 0.68 ? 0.98 ? 1.08 ? ns t ht t -register hold time 0.88 ? 0.68 ? 0.98 ? 1.08 ? ns t sir d-input register setup time (global clock) 0.82 ? 1.37 ? 1.27 ? 1.27 ? ns t sir_pt d-input register setup time (product term clock) 1.45 ? 1.45 ? 1.45 ? 1.45 ? ns t hir d-input register hold time (global clock) 0.88 ? 0.63 ? 0.73 ? 0.73 ? ns t hir_pt d-input register hold time (product term clock) 0.88 ? 0.63 ? 0.73 ? 0.73 ? ns t coi register clock to output/feedback mux time ? 0.52 ? 0.52 ? 0.52 ? 0.52 ns t ces clock enable setup time 2.25 ? 2.25 ? 2.25 ? 2.25 ? ns t ceh clock enable hold time 1.88 ? 1.88 ? 1.88 ? 1.88 ? ns t sl latch setup time (global clock) 0.92 ? 1.12 ? 1.02 ? 0.92 ? ns t sl_pt latch setup time (product term clock) 1.42 ? 1.32 ? 1.32 ? 1.32 ? ns t hl latch hold time 1.17 ? 1.17 ? 1.17 ? 1.17 ? ns t goi latch gate to output/feedback mux time ? 0.33 ? 0.33 ? 0.33 ? 0.33 ns
lattice semiconductor ispmach 4000v/b/c/z family data sheet 27 t pdli propagation delay through tr ansparent latch to output/ f eedback mux ? 0.25 ? 0.25 ? 0.25 ? 0.25 ns t sri asynchronous reset or set to output/feedback mux delay 0.28 ? 0.28 ? 0.28 ? 0.28 ? ns t srr asynchronous reset or set recovery time 1.67 ? 1.67 ? 1.67 ? 1.67 ? ns control delays t bclk glb pt clock delay ? 1.12 ? 1.12 ? 1.12 ? 1.12 ns t ptclk macrocell pt clock delay ? 0.87 ? 0.87 ? 0.87 ? 0.87 ns t bsr block pt set/reset delay ? 1.83 ? 1.83 ? 1.83 ? 1.83 ns t ptsr macrocell pt set/reset delay ? 1.11 ? 1.41 ? 1.51 ? 1.61 ns t gptoe global pt oe delay ? 2.83 ? 4.13 ? 5.33 ? 5.33 ns t ptoe macrocell pt oe delay ? 1.83 ? 2.13 ? 2.33 ? 2.83 ns timing v.3.1 note: internal timing parameters are not tested and are for reference only. refer to timing model in this data sheet for furthe r details. ispmach 4000v/b/c internal timing parameters (cont.) over recommended operating conditions p arameter description -2.5 -2.7 -3 -3.5 units
lattice semiconductor ispmach 4000v/b/c/z family data sheet 28 ispmach 4000v/b/c internal timing parameters over recommended operating conditions p arameter description -5 -75 -10 units min. max. min. max. min. max. in/out delays t in input buffer delay ? 0.95 ? 1.50 ? 2.00 ns t goe global oe pin delay ? 4.04 ? 6.04 ? 7.04 ns t gclk_in global clock input buffer delay ? 1.83 ? 2.28 ? 3.28 ns t buf delay through output buffer ? 1.00 ? 1.50 ? 1.50 ns t en output enable time ? 0.96 ? 0.96 ? 0.96 ns t dis output disable time ? 0.96 ? 0.96 ? 0.96 ns routing/glb delays t r oute delay through grp ? 1.51 ? 2.26 ? 3.26 ns t mcell macrocell delay ? 1.05 ? 1.45 ? 1.95 ns t inreg input buffer to macrocell register delay ? 0.56 ? 0.96 ? 1.46 ns t fbk internal feedback delay ? 0.00 ? 0.00 ? 0.00 ns t pdb 5-pt bypass propagation delay ? 1.54 ? 2.24 ? 3.24 ns t pdi macrocell propagation delay ? 0.94 ? 1.24 ? 1.74 ns register/latch delays t s d-register setup time (global clock) 1.32 ? 1.57 ? 1.57 ? ns t s_pt d-register setup time (product term clock) 1.32 ? 1.32 ? 1.32 ? ns t st t -register setup time (global clock) 1.52 ? 1.77 ? 1.77 ? ns t st_pt t -register setup time (product term clock) 1.32 ? 1.32 ? 1.32 ? ns t h d-register hold time 1.68 ? 2.93 ? 3.93 ? ns t ht t -register hold time 1.68 ? 2.93 ? 3.93 ? ns t sir d-input register setup time (global clock) 1.52 ? 1.57 ? 1.57 ? ns t sir_pt d-input register setup time (product term clock) 1.45 ? 1.45 ? 1.45 ? ns t hir d-input register hold time (global clock) 0.68 ? 1.18 ? 1.18 ? ns t hir_pt d-input register hold time (product term clock) 0.68 ? 1.18 ? 1.18 ? ns t coi register clock to output/feedback mux time ? 0.52 ? 0.67 ? 1.17 ns t ces clock enable setup time 2.25 ? 2.25 ? 2.25 ? ns t ceh clock enable hold time 1.88 ? 1.88 ? 1.88 ? ns t sl latch setup time (global clock) 1.32 ? 1.57 ? 1.57 ? ns t sl_pt latch setup time (product term clock) 1.32 ? 1.32 ? 1.32 ? ns t hl latch hold time 1.17 ? 1.17 ? 1.17 ? ns t goi latch gate to output/feedback mux time ? 0.33 ? 0.33 ? 0.33 ns t pdli propagation delay through transparent latch to output/ f eedback mux ? 0.25 ? 0.25 ? 0.25 ns t sri asynchronous reset or set to output/feedback mux delay 0.28 ? 0.28 ? 0.28 ? ns t srr asynchronous reset or set recovery time 1.67 ? 1.67 ? 1.67 ? ns control delays t bclk glb pt clock delay ? 1.12 ? 1.12 ? 0.62 ns t ptclk macrocell pt clock delay ? 0.87 ? 0.87 ? 0.87 ns t bsr glb pt set/reset delay ? 1.83 ? 1.83 ? 1.83 ns t ptsr macrocell pt set/reset delay ? 2.51 ? 3.41 ? 3.41 ns
lattice semiconductor ispmach 4000v/b/c/z family data sheet 29 t gptoe global pt oe delay ? 5.58 ? 5.58 ? 5.78 ns t ptoe macrocell pt oe delay ? 3.58 ? 4.28 ? 4.28 ns timing v.3.1 note: internal timing parameters are not tested and are for reference only. refer to timing model in this data sheet for furthe r details. ispmach 4000v/b/c internal timing parameters (cont.) over recommended operating conditions p arameter description -5 -75 -10 units min. max. min. max. min. max.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 30 ispmach 4032z internal timing parameters 1 over recommended operating conditions p arameter description -35 -5 -75 units min. max. min. max. min. max. in/out delays t in input buffer delay ? 0.75 ? 0.95 ? 1.50 ns t goe global oe pin delay ? 2.90 ? 3.20 ? 4.96 ns t gclk_in global clock input buffer delay ? 1.50 ? 1.90 ? 2.28 ns t buf delay through output buffer ? 0.65 ? 0.90 ? 1.50 ns t en output enable time ? 1.60 ? 1.80 ? 2.04 ns t dis output disable time ? 1.35 ? 1.60 ? 2.96 ns routing/glb delays t r oute delay through grp ? 1.70 ? 2.25 ? 2.26 ns t mcell macrocell delay ? 0.65 ? 1.00 ? 1.45 ns t inreg input buffer to macrocell register delay ? 0.91 ? 0.75 ? 0.65 ns t fbk internal feedback delay ? 0.35 ? 0.50 ? 0.70 ns t pdb 5-pt bypass propagation delay ? 0.40 ? 0.90 ? 2.24 ns t pdi macrocell propagation delay ? 0.25 ? 0.35 ? 1.24 ns register/latch delays t s d-register setup time (global clock) 0.60 ? 0.70 ? 1.57 ? ns t s_pt d-register setup time (product term clock) 1.55 ? 1.50 ? 1.65 ? ns t st t -register setup time (global clock) 0.90 ? 0.90 ? 1.77 ? ns t st_pt t -register setup time (product term clock) 1.75 ? 1.50 ? 1.32 ? ns t h d-register hold time 1.60 ? 2.30 ? 2.93 ? ns t ht t -resister hold time 1.60 ? 2.30 ? 2.93 ? ns t sir d-input register setup time (global clock) 0.84 ? 1.40 ? 1.83 ? ns t sir_pt d-input register setup time (product term clock) 1.45 ? 1.45 ? 1.45 ? ns t hir d-input register hold time (global clock) 1.16 ? 0.80 ? 0.87 ? ns t hir_pt d-input register hold time (product term clock) 0.88 ? 1.00 ? 1.18 ? ns t coi register clock to output/feedback mux time ? 0.45 ? 0.55 ? 0.67 ns t ces clock enable setup time 1.00 ? 1.40 ? 2.00 ? ns t ceh clock enable hold time 0.00 ? 0.00 ? 0.00 ? ns t sl latch setup time (global clock) 0.65 ? 1.02 ? 1.57 ? ns t sl_pt latch setup time (product term clock) 1.75 ? 1.32 ? 1.32 ? ns t hl latch hold time 1.40 ? 1.17 ? 1.17 ? ns t goi latch gate to output/feedback mux time ? 0.40 ? 0.33 ? 0.33 ns t pdli propagation delay through transparent latch to output/feed- back mux ? 0.30 ? 0.25 ? 0.25 ns t sri asynchronous reset or set to output/feedback mux delay ? 1.00 ? 0.28 ? 0.28 ns t srr asynchronous reset or set recovery delay ? 2.00 ? 1.67 ? 1.67 ns control delays t bclk glb pt clock delay ? 1.50 ? 1.12 ? 1.12 ns t ptclk macrocell pt clock delay ? 1.70 ? 0.87 ? 0.87 ns t bsr glb pt set/reset delay ? 1.10 ? 1.83 ? 1.83 ns t ptsr macrocell pt set/reset delay ? 0.50 ? 1.87 ? 3.41 ns t gptoe global pt oe delay ? 2.45 ? 3.00 ? 3.20 ns
lattice semiconductor ispmach 4000v/b/c/z family data sheet 31 t ptoe macrocell pt oe delay ? 2.95 ? 3.00 ? 3.20 ns timing v.1.2 1. preliminary information. note: internal timing parameters are not tested and are for reference only. refer to timing model in this data sheet for furthe r details. ispmach 4032z internal timing parameters 1 (cont.) over recommended operating conditions p arameter description -35 -5 -75 units min. max. min. max. min. max.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 32 ispmach 4000v/b/c timing adders 1 adder t ype base p arameter description -25 -27 -3 -35 units min. max. min. max. min. max. min. max. optional delay adders t indio t inreg input register delay ? 0.95 ? 1.00 ? 1.00 ? 1.00 ns t exp t mcell product term expander delay ? 0.33 ? 0.33 ? 0.33 ? 0.33 ns t orp ? output routing pool delay ? 0.05 ? 0.05 ? 0.05 ? 0.05 ns t bla t r oute additional block loading adder ? 0.03 ? 0.05 ? 0.05 ? 0.05 ns t ioi input adjusters l vttl_in t in , t gclk_in , t goe using lvttl standard ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns l vcmos33_in t in , t gclk_in , t goe using lvcmos 3.3 standard ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns l vcmos25_in t in , t gclk_in , t goe using lvcmos 2.5 standard ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns l vcmos18_in t in , t gclk_in , t goe using lvcmos 1.8 standard ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns pci_in t in , t gclk_in , t goe using pci compatible input ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns t ioo output adjusters l vttl_out t buf , t en , t dis output con gured as ttl buffer ? 0.20 ? 0.20 ? 0.20 ? 0.20 ns l vcmos33_out t buf , t en , t dis output con gured as 3.3v buffer ? 0.20 ? 0.20 ? 0.20 ? 0.20 ns l vcmos25_out t buf , t en , t dis output con gured as 2.5v buffer ? 0.10 ? 0.10 ? 0.10 ? 0.10 ns l vcmos18_out t buf , t en , t dis output con gured as 1.8v buffer ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns pci_out t buf , t en , t dis output con gured as pci compatible buffer ? 0.20 ? 0.20 ? 0.20 ? 0.20 ns slow slew t buf , t en output con gured for slow slew rate ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns note: open drain timing is the same as corresponding lvcmos timing. timing v.3.1 1. refer to technical note tn1004: ispmach 4000 timing model design and usage guidelines f or information regarding use of these adders.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 33 ispmach 4000v/b/c timing adders 1 adder t ype base p arameter description -5 -75 -10 units min. max. min. max. min. max. optional delay adders t indio t inreg input register delay ? 1.00 ? 1.00 ? 1.00 ns t exp t mcell product term expander delay ? 0.33 ? 0.33 ? 0.33 ns t orp ? output routing pool delay ? 0.05 ? 0.05 ? 0.05 ns t bla t r oute additional block loading adder ? 0.05 ? 0.05 ? 0.05 ns t ioi input adjusters l vttl_in t in , t gclk_in , t goe using lvttl standard ? 0.60 ? 0.60 ? 0.60 ns l vcmos33_in t in , t gclk_in , t goe using lvcmos 3.3 standard ? 0.60 ? 0.60 ? 0.60 ns l vcmos25_in t in , t gclk_in , t goe using lvcmos 2.5 standard ? 0.60 ? 0.60 ? 0.60 ns l vcmos18_in t in , t gclk_in , t goe using lvcmos 1.8 standard ? 0.00 ? 0.00 ? 0.00 ns pci_in t in , t gclk_in , t goe using pci compatible input ? 0.60 ? 0.60 ? 0.60 ns t ioo output adjusters l vttl_out t buf , t en , t dis output con gured as ttl buffer ? 0.20 ? 0.20 ? 0.20 ns l vcmos33_out t buf , t en , t dis output con gured as 3.3v buffer ? 0.20 ? 0.20 ? 0.20 ns l vcmos25_out t buf , t en , t dis output con gured as 2.5v buffer ? 0.10 ? 0.10 ? 0.10 ns l vcmos18_out t buf , t en , t dis output con gured as 1.8v buffer ? 0.00 ? 0.00 ? 0.00 ns pci_out t buf , t en , t dis output con gured as pci compatible b uffer ? 0.20 ? 0.20 ? 0.20 ns slow slew t buf , t en output con gured for slow slew rate ? 1.00 ? 1.00 ? 1.00 ns note: open drain timing is the same as corresponding lvcmos timing. timing v.3.1 1. refer to technical note tn1004: ispmach 4000 timing model design and usage guidelines f or information regarding use of these adders.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 34 ispmach 4032z timing adders 1, 2 adder t ype base p arameter description -35 -5 -7 units min. max. min. max. min. max. optional delay adders t indio t inreg input register delay ? 1.00 ? 1.00 ? 1.00 ns t exp t mcell product term expander delay ? 0.40 ? 0.50 ? 0.50 ns t orp ? output routing pool delay ? 0.40 ? 0.05 ? 0.05 ns t bla t r oute additional block loading adder ? 0.04 ? 0.05 ? 0.05 ns t ioi input adjusters l vttl_in t in, t gclk_in, t goe using lvttl standard ? 0.70 ? 0.70 ? 0.70 ns l vcmos33_in t in, t gclk_in, t goe using lvcmos 3.3 standard ? 0.70 ? 0.70 ? 0.70 ns l vcmos25_in t in, t gclk_in, t goe using lvcmos 2.5 standard ? 0.40 ? 0.40 ? 0.40 ns l vcmos18_in t in, t gclk_in, t goe using lvcmos 1.8 standard ? 0.00 ? 0.00 ? 0.00 ns pci_in t in, t gclk_in, t goe using pci compatible input ? 0.70 ? 0.70 ? 0.70 ns t ioo output adjusters l vttl_out t buf, t en, t dis output con gured as ttl b uffer ? 0.70 ? 0.70 ? 0.70 ns l vcmos33_out t buf, t en, t dis output con gured as 3.3v b uffer ? 0.70 ? 0.70 ? 0.70 ns l vcmos25_out t buf, t en, t dis output con gured as 2.5v b uffer ? 0.40 ? 0.40 ? 0.40 ns l vcmos18_out t buf, t en, t dis output con gured as 1.8v b uffer ? 0.00 ? 0.00 ? 0.00 ns pci_out t buf, t en, t dis output con gured as pci compatible buffer ? 0.70 ? 0.70 ? 0.70 ns slow slew t buf, t en output con gured for slow slew rate ? 1.00 ? 1.00 ? 1.00 ns timing v.1.2 1. preliminary information. 2. refer to technical note tn 1004: ispmach 4000 timing model design and usage guidelines for information regarding use of these adders. note: open drain timing is the same as corresponding lvcmos timing.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 35 boundary scan waveforms and timing speci cations symbol parameter min. max. units t btcp tck [bscan test] clock cycle 40 ? ns t btch tck [bscan test] pulse width high 20 ? ns t btcl tck [bscan test] pulse width low 20 ? ns t btsu tck [bscan test] setup time 8 ? ns t bth tck [bscan test] hold time 10 ? ns t brf tck [bscan test] rise and fall time 50 ? mv/ns t btco t ap controller falling edge of clock to valid output ? 10 ns t btoz t ap controller falling edge of clock to data output disable ? 10 ns t btvo t ap controller falling edge of clock to data output enable ? 10 ns t btcpsu bscan test capture register setup time 8 ? ns t btcph bscan test capture register hold time 10 ? ns t btuco bscan test update reg, falling edge of clock to valid output ? 25 ns t btuoz bscan test update reg, falling edge of clock to output disable ? 25 ns t btuov bscan test update reg, falling edge of clock to output enable ? 25 ns
lattice semiconductor ispmach 4000v/b/c/z family data sheet 36 po wer consumption po wer estimation coef cients 1 device a b ispmach 4032v/b 11.3 0.010 ispmach 4032c 1.3 0.010 ispmach 4064v/b 11.5 0.010 ispmach 4064c 1.5 0.010 ispmach 4128v/b 11.5 0.011 ispmach 4128c 1.5 0.011 ispmach 4256v/b 12 0.011 ispmach 4256c 2 0.011 ispmach 4384v/b 12.5 0.013 ispmach 4384c 2.5 0.013 ispmach 4512v/b 13 0.013 ispmach 4512c 3 0.013 ispmach 4032zc 2 0.020 0.010 ispmach 4064zc 3 ispmach 4128zc 3 ispmach 4256zc 3 1. for further information about the use of these coef cients, refer to technical note tn1005, po w er estimation in ispmach 4000v/b/c devices. 2. preliminary information. 3. advance information. 0 100 50 50 100 200 150 250 150 200 250 300 350 400 frequency (mhz) i cc (ma) i cc (ma) note: the devices are configured with maximum number of 16-bit counters, typical current at 1.8v, 25 c. 150 200 300 250 100 50 0 4032v/b 4064v/b 4128v/b 4384v/b 4256v/b 4512v/b ispmach 4000c typical i cc vs. frequency note: the devices are configured with maximum number of 16-bit counters, typical current at 3.3v, 2.5v, 25 c. 4032c 4064c 4128c 4384c 4256c 4512c ispmach 4000v/b typical i cc vs. frequency 4032zc 60 80 100 40 20 0100 50 150 200 250 300 350 400 frequency (mhz) i cc (ma) 150 200 300 250 100 50 0 note: the devices are configured with maximum number of 16-bit counters, typical current at 1.8v, 25 c. ispmach 4000z typical i cc vs. frequency (preliminary information) 0300 frequency (mhz) 0
lattice semiconductor ispmach 4000v/b/c/z family data sheet 37 switching test conditions figure 12 shows the output test load that is used for ac testing. the speci c values for resistance, capacitance, v oltage, and other test conditions are shown in table 11. figure 12. output test load, lvttl and lvcmos standards ta b le 11. test fixture required components t est condition r 1 r 2 c l 1 timing ref. v cco l vcmos i/o, (l -> h, h -> l) 106 ? 106 ? 35pf l vcmos 3.3 = 1.5v lvcmos 3.3 = 3.0v l vcmos 2.5 = v cco /2 lvcmos 2.5 = 2.3v l vcmos 1.8 = v cco /2 lvcmos 1.8 = 1.65v l vcmos i/o (z -> h) 106 ? 35pf 1.5v 3.0v l vcmos i/o (z -> l) 106 ? 35pf 1.5v 3.0v l vcmos i/o (h -> z) 106 ? 5pf v oh - 0.3 3.0v l vcmos i/o (l -> z) 106 ? 5pf v ol + 0.3 3.0v 1. c l includes test xtures and probe capacitance. v cco r 1 r 2 c l dut test point 0213a/ispm4 k
lattice semiconductor ispmach 4000v/b/c/z family data sheet 38 signal descriptions signal names description tms input ? this pin is the ieee 1149.1 test mode select input, which is used to control the state machine tck input ? this pin is the ieee 1149.1 test clock input pin, used to clock through the state machine tdi input ? this pin is the ieee 1149.1 test data in pin, used to load data tdo output ? this pin is the ieee 1149.1 test data out pin used to shift data out goe0/io, goe1/io these pins are con gured to be either global output enable input or as general i/o pins gnd ground nc not connected v cc the power supply pins for logic core clk0/i, clk1/i, clk2/i, clk3/i these pins are con gured to be either clk input or as an input v cco0 , v cco1 the power supply pins for each i/o bank yzz input/output 1 ? these are the general purpose i/o used by the logic array. y is glb reference (alpha) and z is macrocell reference (numeric). z: 0-15 ispmach 4032 y: a-b ispmach 4064 y: a-d ispmach 4128 y: a-h ispmach 4256 y: a-p ispmach 4384 y: a-p, ax-hx ispmach 4512 y: a-p, ax-px 1. in some packages, certain i/o are only available for use as inputs. see the signal connections table for details.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 39 ispmach 4000v/b/c/z power supply and nc connections 1 signal 44 tqfp 4 48 tqfp 4 56 csbga 7 100 tqfp 4 128 tqfp 4 144 tqfp 4 176 tqfp 4 256 fpbga 2, 3, 7 vcc 11, 33 12, 36 k2, a9 25, 40, 75, 90 32, 51, 96, 115 36, 57, 108, 129 42, 69, 88, 130, 157, 176 b2, b15, g8, g9, k8, k9, r2, r15 vcco0 6 6 f3 13, 33, 95 3, 17, 30, 41, 122 3, 19, 34, 47, 136 4, 22, 40, 56, 166 d6, f4, h7, j7, l4, n6 vcco1 28 30 e8 45, 63, 83 58, 67, 81, 94, 105 64, 75, 91, 106, 119 78, 92, 110, 128, 144 d11, f13, h10, j10, l13, n11 gnd 12, 34 13, 37 h3, c8 1, 26, 51, 76 1, 33, 65, 97 1, 37, 73, 109 2, 46 5 , 65, 90, 134, 153 a1, a16, c6, c11, f3, f14, g7, g10, h8, h9, j8, j9, k7, k10, l3, l14, p6, p11, t1, t16 gnd (bank 0) 55 d3 7, 18, 32, 96 10, 24, 40, 113, 123 10, 18 6 , 27, 46, 127, 137 13, 31, 55, 155, 167 gnd (bank 1) 27 29 g8 46, 57, 68, 82 49, 59, 74, 88, 104 55, 65, 82, 90 6 , 99, 118 67, 79, 101, 119, 143 nc ? ? 4032z : a8, b10, e1, e3, f8, f10, j1, k3 ?? 4128v : 17, 20, 38, 45, 72, 89, 92, 110, 117, 144 4256v : 18, 90 1, 43, 44, 45, 89, 131, 132, 133 4256v/b/c, 128 i/o: a4, a5, a6, a11, a12, a13, a15, b5, b6, b11, b12, b14, c7, d1, d4, d5, d10, d12, d16, e1, e2, e4, e5, e7, e10, e13, e14, e15, e16, f1, f2, f15, f16, g1, g4, g5, g6, g12, g13, g14, j11, k3, k4, k15, l1, l2, l12, l15, l16, m1, m2, m3, m4, m5, m12, m13, m15, m16, n1, n2, n7, n10, n12, n14, p5, p12, r4, r5, r6, r11, r12, r16, t2, t4, t5, t6, t11, t12, t13, t15 4256v/b/c, 160 i/o: a5, a12, a15, b5, b6, b11, b12, b14, d4, d5, d12, e1, e4, e5, e13, e15, e16, f1, f2, f15, g1, g5, g12, g14, l1, l2, l12, l15, l16, m1, m2, m3, m12, m16, n1, n12, n14, p5, r4, r5, r6, r11, r12, r16, t4, t5, t12, t15 4384v/b/c: b5, b12, d5, d12, e1, e15, e16, f2, l12, m1, m2, m16, n12, r5, r12, t4 4512v/b/c: none 1. all grounds must be electrically connected at the board level. however, for the purposes of i/o current loading, grounds are associated with the bank shown. 2. internal gnds and i/o gnds (bank 0/1) are connected inside package. 3. v cco balls connect to two power planes within the package, one for v cco0 and one for v cco1 . 4. pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise. 5. ispmach 4384v/b/c pin 46 is tied to gnd (bank 0). 6. ispmach 4128v only. 7. pin orientation a1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and nu merical order ascending horizontally.
lattice semiconductor ispmach 4000v/b/c/z family data sheet 40 ispmach 4032v/b/c and 4064v/b/c logic signal connections: 44-pin tqfp pin number bank number ispmach 4032v/b/c ispmach 4064v/b/c glb/mc/pad orp glb/mc/pad orp 1-tdi- tdi - 20a5 a^5 a10 a^5 30a6 a^6 a12 a^6 40a7 a^7 a14 a^7 5 0 gnd (bank 0) - gnd (bank 0) - 6 0 vcco (bank 0) - vcco (bank 0) - 70a8 a^8 b0 b^0 80a9 a^9 b2 b^1 90 a10 a^10 b4 b^2 10 - tck - tck - 11 - vcc - vcc - 12 - gnd - gnd - 13 0 a12 a^12 b8 b^4 14 0 a13 a^13 b10 b^5 15 0 a14 a^14 b12 b^6 16 0 a15 a^15 b14 b^7 17 1 clk2/i - clk2/i - 18 1 b0 b^0 c0 c^0 19 1 b1 b^1 c2 c^1 20 1 b2 b^2 c4 c^2 21 1 b3 b^3 c6 c^3 22 1 b4 b^4 c8 c^4 23 - tms - tms - 24 1 b5 b^5 c10 c^5 25 1 b6 b^6 c12 c^6 26 1 b7 b^7 c14 c^7 27 1 gnd (bank 1) - gnd (bank 1) - 28 1 vcco (bank 1) - vcco (bank 1) - 29 1 b8 b^8 d0 d^0 30 1 b9 b^9 d2 d^1 31 1 b10 b^10 d4 d^2 32 - tdo - tdo - 33 - vcc - vcc - 34 - gnd - gnd - 35 1 b12 b^12 d8 d^4 36 1 b13 b^13 d10 d^5 37 1 b14 b^14 d12 d^6 38 1 b15/goe1 b^15 d14/goe1 d^7 39 0 clk0/i - clk0/i - 40 0 a0/goe0 a^0 a0/goe0 a^0 41 0 a1 a^1 a2 a^1
lattice semiconductor ispmach 4000v/b/c/z family data sheet 41 42 0 a2 a^2 a4 a^2 43 0 a3 a^3 a6 a^3 44 0 a4 a^4 a8 a^4 ispmach 4032v/b/c/z and 4064v/b/c/z logic signal connections: 48-pin tqfp pin number bank number ispmach 4032v/b/c ispmach 4064v/b/c ispmach 4064z glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp 1- tdi - tdi - tdi - 20 a5 a^5 a10 a^5 a8 a^8 30 a6 a^6 a12 a^6 a10 a^10 40 a7 a^7 a14 a^7 a11 a^11 5 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - 6 0 vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - 70 a8 a^8 b0 b^0 b15 b^15 80 a9 a^9 b2 b^1 b12 b^12 90 a10 a^10 b4 b^2 b10 b^10 10 0 a11 a^11 b6 b^6 b8 b^8 11 - tck - tck - tck - 12 - vcc - vcc - vcc - 13 - gnd - gnd - gnd - 14 0 a12 a^12 b8 b^4 b6 b^6 15 0 a13 a^13 b10 b^5 b4 b^4 16 0 a14 a^14 b12 b^6 b2 b^2 17 0 a15 a^15 b14 b^7 b0 b^0 18 0 clk1/i - clk1/i - clk1/i - 19 1 clk2/i - clk2/i - clk2/i - 20 1 b0 b^0 c0 c^0 c0 c^0 21 1 b1 b^1 c2 c^1 c1 c^1 22 1 b2 b^2 c4 c^2 c2 c^2 23 1 b3 b^3 c6 c^3 c4 c^4 24 1 b4 b^4 c8 c^4 c6 c^6 25 - tms - tms - tms - 26 1 b5 b^5 c10 c^5 c8 c^8 27 1 b6 b^6 c12 c^6 c10 c^10 28 1 b7 b^7 c14 c^7 c11 c^11 29 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - 30 1 vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - 31 1 b8 b^8 d0 d^0 d15 d^15 32 1 b9 b^9 d2 d^1 d12 d^12 ispmach 4032v/b/c and 4064v/b/c logic signal connections: 44-pin tqfp (cont.) pin number bank number ispmach 4032v/b/c ispmach 4064v/b/c glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 42 33 1 b10 b^10 d4 d^2 d10 d^10 34 1 b11 b^11 d6 d^3 d8 d^8 35 - tdo - tdo - tdo - 36 - vcc - vcc - vcc - 37 - gnd - gnd - gnd - 38 1 b12 b^12 d8 d^4 d6 d^6 39 1 b13 b^13 d10 d^5 d4 d^4 40 1 b14 b^14 d12 d^6 d2 d^2 41 1 b15/goe1 b^15 d14/goe1 d^7 d0/goe1 d^0 42 1 clk3/i - clk3/i - clk3/i - 43 0 clk0/i - clk0/i - clk0/i - 44 0 a0/goe0 a^0 a0/goe0 a^0 a0/goe0 a^0 45 0 a1 a^1 a2 a^1 a1 a^1 46 0 a2 a^2 a4 a^2 a2 a^2 47 0 a3 a^3 a6 a^3 a4 a^4 48 0 a4 a^4 a8 a^4 a6 a^6 ispmach 4032z and 4064z logic signal connections: 56-ball csbga ball number bank number ispmach 4032z ispmach 4064z glb/mc/pad orp glb/mc/pad orp b1 - tdi - tdi - c3 0 a5 a^5 a8 a^8 c1 0 a6 a^6 a10 a^10 d1 0 a7 a^7 a11 a^11 d3 0 gnd (bank 0) - gnd (bank 0) - e3 0 nc - a15/i a^15 e1 0 n c -i- f3 0 vcco (bank 0) - vcco (bank 0) - f1 0 a8 a^8 b15 b^15 g3 0 a9 a^9 b12 b^12 g1 0 a10 a^10 b10 b^10 h1 0 a11 a^11 b8 b^8 j1 0 n c -i- k1 - tck - tck - k2 - vcc - vcc - h3 - gnd - gnd - k3 - i - k4 0 a12 a^12 b6 b^6 h4 0 a13 a^13 b4 b^4 h5 0 a14 a^14 b2 b^2 ispmach 4032v/b/c/z and 4064v/b/c/z logic signal connections: 48-pin tqfp (cont.) pin number bank number ispmach 4032v/b/c ispmach 4064v/b/c ispmach 4064z glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 43 k5 0 a15 a^15 b0 b^0 h6 0 clk1/i - clk1/i - k6 1 clk2/i - clk2/i - h7 1 b0 b^0 c0 c^0 k7 1 b1 b^1 c1 c^1 k8 1 b2 b^2 c2 c^2 k9 1 b3 b^3 c4 c^4 k10 1 b4 b^4 c6 c^6 j10 - tms - tms - h8 1 b5 b^5 c8 c^8 h10 1 b6 b^6 c10 c^10 g10 1 b7 b^7 c11 c^11 g8 1 gnd (bank 1) - gnd (bank 1) - f8 1 nc - c12/i c12 f10 1 nc - i - e8 1 vcco (bank 1) - vcco (bank 1) - e10 1 b8 b^8 d15 d^15 d8 1 b9 b^9 d12 d^12 d10 1 b10 b^10 d10 d^10 c10 1 b11 b^11 d8 d^8 b10 1 nc - i - a10 - tdo - tdo - a9 - vcc - vcc - c8 - gnd - gnd - a8 1 n c -i- a7 1 b12 b^12 d6 d^6 c7 1 b13 b^13 d4 d^4 c6 1 b14 b^14 d2 d^2 a6 1 b15/goe1 b^15 d0/goe1 d^0 c5 1 clk3/i - clk3/i - a5 0 clk0/i - clk0/i - c4 0 a0/goe0 a^0 a0/goe0 a^0 a4 0 a1 a^1 a1 a^1 a3 0 a2 a^2 a2 a^2 a2 0 a3 a^3 a4 a^4 a1 0 a4 a^4 a6 a^6 ispmach 4032z and 4064z logic signal connections: 56-ball csbga (cont.) ball number bank number ispmach 4032z ispmach 4064z glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 44 ispmach 4064v/b/c/z, 4128v/b/c/z, 4256v/b/c logic signal connections: 100-pin tqfp pin number bank number ispmach 4064v/b/c/z ispmach 4128v/b/c/z ispmach 4256v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp 1-gnd- gnd - gnd - 2-tdi- tdi - tdi - 30a8 a^8 b0 b^0 c12 c^6 40a9 a^9 b2 b^2 c10 c^5 50 a10 a^10 b4 b^4 c6 c^3 60 a11 a^11 b6 b^6 c2 c^1 7 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - 80 a12 a^12 b8 b^8 d12 d^6 90 a13 a^13 b10 b^10 d10 d^5 10 0 a14 a^14 b12 b^12 d6 d^3 11 0 a15 a^15 b13 b^13 d4 d^2 12* 0 i - i - i - 13 0 vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - 14 0 b15 b^15 c14 c^14 e4 e^2 15 0 b14 b^14 c12 c^12 e6 e^3 16 0 b13 b^13 c10 c^10 e10 e^5 17 0 b12 b^12 c8 c^8 e12 e^6 18 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - 19 0 b11 b^11 c6 c^6 f2 f^1 20 0 b10 b^10 c5 c^5 f6 f^3 21 0 b9 b^9 c4 c^4 f10 f^5 22 0 b8 b^8 c2 c^2 f12 f^6 23* 0 i - i - i - 24 - tck - tck - tck - 25 - vcc - vcc - vcc - 26 - gnd - gnd - gnd - 27* 0 i - i - i - 28 0 b7 b^7 d13 d^13 g12 g^6 29 0 b6 b^6 d12 d^12 g10 g^5 30 0 b5 b^5 d10 d^10 g6 g^3 31 0 b4 b^4 d8 d^8 g2 g^1 32 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - 33 0 vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - 34 0 b3 b^3 d6 d^6 h12 h^6 35 0 b2 b^2 d4 d^4 h10 h^5 36 0 b1 b^1 d2 d^2 h6 h^3 37 0 b0 b^0 d0 d^0 h2 h^1 38 0 clk1/i - clk1/i - clk1/i - 39 1 clk2/i - clk2/i - clk2/i - 40 - vcc - vcc - vcc - 41 1 c0 c^0 e0 e^0 i2 i^1
lattice semiconductor ispmach 4000v/b/c/z family data sheet 45 42 1 c1 c^1 e2 e^2 i6 i^3 43 1 c2 c^2 e4 e^4 i10 i^5 44 1 c3 c^3 e6 e^6 i12 i^6 45 1 vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - 46 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - 47 1 c4 c^4 e8 e^8 j2 j^1 48 1 c5 c^5 e10 e^10 j6 j^3 49 1 c6 c^6 e12 e^12 j10 j^5 50 1 c7 c^7 e14 e^14 j12 j^6 51 - gnd - gnd - gnd - 52 - tms - tms - tms - 53 1 c8 c^8 f0 f^0 k12 k^6 54 1 c9 c^9 f2 f^2 k10 k^5 55 1 c10 c^10 f4 f^4 k6 k^3 56 1 c11 c^11 f6 f^6 k2 k^1 57 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - 58 1 c12 c^12 f8 f^8 l12 l^6 59 1 c13 c^13 f10 f^10 l10 l^5 60 1 c14 c^14 f12 f^12 l6 l^3 61 1 c15 c^15 f13 f^13 l4 l^2 62* 1 i - i - i - 63 1 vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - 64 1 d15 d^15 g14 g^14 m4 m^2 65 1 d14 d^14 g12 g^12 m6 m^3 66 1 d13 d^13 g10 g^10 m10 m^5 67 1 d12 d^12 g8 g^8 m12 m^6 68 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - 69 1 d11 d^11 g6 g^6 n2 n^1 70 1 d10 d^10 g5 g^5 n6 n^3 71 1 d9 d^9 g4 g^4 n10 n^5 72 1 d8 d^8 g2 g^2 n12 n^6 73* 1 i - i - i - 74 - tdo - tdo - tdo - 75 - vcc - vcc - vcc - 76 - gnd - gnd - gnd - 77* 1 i - i - i - 78 1 d7 d^7 h13 h^13 o12 o^6 79 1 d6 d^6 h12 h^12 o10 o^5 80 1 d5 d^5 h10 h^10 o6 o^3 81 1 d4 d^4 h8 h^8 o2 o^1 82 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - ispmach 4064v/b/c/z, 4128v/b/c/z, 4256v/b/c logic signal connections: 100-pin tqfp (cont.) pin number bank number ispmach 4064v/b/c/z ispmach 4128v/b/c/z ispmach 4256v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 46 83 1 vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - 84 1 d3 d^3 h6 h^6 p12 p^6 85 1 d2 d^2 h4 h^4 p10 p^5 86 1 d1 d^1 h2 h^2 p6 p^3 87 1 d0/goe1 d^0 h0/goe1 h^0 p2/oe1 p^1 88 1 clk3/i - clk3/i - clk3/i - 89 0 clk0/i - clk0/i - clk0/i - 90 - vcc - vcc - vcc - 91 0 a0/goe0 a^0 a0/goe0 a^0 a2/goe0 a^1 92 0 a1 a^1 a2 a^2 a6 a^3 93 0 a2 a^2 a4 a^4 a10 a^5 94 0 a3 a^3 a6 a^6 a12 a^6 95 0 vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - 96 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - 97 0 a4 a^4 a8 a^8 b2 b^1 98 0 a5 a^5 a10 a^10 b6 b^3 99 0 a6 a^6 a12 a^12 b10 b^5 100 0 a7 a^7 a14 a^14 b12 b^6 *this pin is input only. ispmach 4128v/b/c logic signal connections: 128-pin tqfp pin number bank number ispmach 4128v/b/c glb/mc/pad orp 10 gnd - 20 tdi - 3 0 vcco (bank 0) - 40b0 b^0 50b1 b^1 60b2 b^2 70b4 b^4 80b5 b^5 90b6 b^6 10 0 gnd (bank 0) - 11 0 b8 b^8 12 0 b9 b^9 13 0 b10 b^10 14 0 b12 b^12 15 0 b13 b^13 16 0 b14 b^14 17 0 vcco (bank 0) - 18 0 c14 c^14 ispmach 4064v/b/c/z, 4128v/b/c/z, 4256v/b/c logic signal connections: 100-pin tqfp (cont.) pin number bank number ispmach 4064v/b/c/z ispmach 4128v/b/c/z ispmach 4256v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 47 19 0 c13 c^13 20 0 c12 c^12 21 0 c10 c^10 22 0 c9 c^9 23 0 c8 c^8 24 0 gnd (bank 0) - 25 0 c6 c^6 26 0 c5 c^5 27 0 c4 c^4 28 0 c2 c^2 29 0 c0 c^0 30 0 vcco (bank 0) - 31 0 tck - 32 0 vcc - 33 0 gnd - 34 0 d14 d^14 35 0 d13 d^13 36 0 d12 d^12 37 0 d10 d^10 38 0 d9 d^9 39 0 d8 d^8 40 0 gnd (bank 0) - 41 0 vcco (bank 0) - 42 0 d6 d^6 43 0 d5 d^5 44 0 d4 d^4 45 0 d2 d^2 46 0 d1 d^1 47 0 d0 d^0 48 0 clk1/i - 49 1 gnd (bank 1) - 50 1 clk2/i - 51 1 vcc - 52 1 e0 e^0 53 1 e1 e^1 54 1 e2 e^2 55 1 e4 e^4 56 1 e5 e^5 57 1 e6 e^6 58 1 vcco (bank 1) - 59 1 gnd (bank 1) - 60 1 e8 e^8 61 1 e9 e^9 ispmach 4128v/b/c logic signal connections: 128-pin tqfp (cont.) pin number bank number ispmach 4128v/b/c glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 48 62 1 e10 e^10 63 1 e12 e^12 64 1 e14 e^14 65 1 gnd - 66 1 tms - 67 1 vcco (bank 1) - 68 1 f0 f^0 69 1 f1 f^1 70 1 f2 f^2 71 1 f4 f^4 72 1 f5 f^5 73 1 f6 f^6 74 1 gnd (bank 1) - 75 1 f8 f^8 76 1 f9 f^9 77 1 f10 f^10 78 1 f12 f^12 79 1 f13 f^13 80 1 f14 f^14 81 1 vcco (bank 1) - 82 1 g14 g^14 83 1 g13 g^13 84 1 g12 g^12 85 1 g10 g^10 86 1 g9 g^9 87 1 g8 g^8 88 1 gnd (bank 1) - 89 1 g6 g^6 90 1 g5 g^5 91 1 g4 g^4 92 1 g2 g^2 93 1 g0 g^0 94 1 vcco (bank 1) - 95 1 tdo - 96 1 vcc - 97 1 gnd - 98 1 h14 h^14 99 1 h13 h^13 100 1 h12 h^12 101 1 h10 h^10 102 1 h9 h^9 103 1 h8 h^8 104 1 gnd (bank 1) - ispmach 4128v/b/c logic signal connections: 128-pin tqfp (cont.) pin number bank number ispmach 4128v/b/c glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 49 105 1 vcco (bank 1) - 106 1 h6 h^6 107 1 h5 h^5 108 1 h4 h^4 109 1 h2 h^2 110 1 h1 h^1 111 1 h0/goe1 h^0 112 1 clk3/i - 113 0 gnd (bank 0) - 114 0 clk0/i - 115 0 vcc - 116 0 a0/goe0 a^0 117 0 a1 a^1 118 0 a2 a^2 119 0 a4 a^4 120 0 a5 a^5 121 0 a6 a^6 122 0 vcco (bank 0) - 123 0 gnd (bank 0) - 124 0 a8 a^8 125 0 a9 a^9 126 0 a10 a^10 127 0 a12 a^12 128 0 a14 a^14 ispmach 4128v and 4256v logic signal connections: 144-pin tqfp pin number bank number ispmach 4128v ispmach 4256v glb/mc/pad orp glb/mc/pad orp 1-gnd- gnd - 2-tdi- tdi - 3 0 vcco (bank 0) - vcco (bank 0) - 40b0 b^0 c12 c^6 50b1 b^1 c10 c^5 60b2 b^2 c8 c^4 70b4 b^4 c6 c^3 80b5 b^5 c4 c^2 90b6 b^6 c2 c^1 10 0 gnd (bank 0) - gnd (bank 0) - 11 0 b8 b^8 d14 d^7 12 0 b9 b^9 d12 d^6 13 0 b10 b^10 d10 d^5 ispmach 4128v/b/c logic signal connections: 128-pin tqfp (cont.) pin number bank number ispmach 4128v/b/c glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 50 14 0 b12 b^12 d8 d^4 15 0 b13 b^13 d6 d^3 16 0 b14 b^14 d4 d^2 17 - nc 2 -i 2 - 18 0 gnd (bank 0) 1 - nc 1 - 19 0 vcco (bank 0) - vcco (bank 0) - 20 0 nc 2 -i 2 - 21 0 c14 c^14 e2 e^1 22 0 c13 c^13 e4 e^2 23 0 c12 c^12 e6 e^3 24 0 c10 c^10 e8 e^4 25 0 c9 c^9 e10 e^5 26 0 c8 c^8 e12 e^6 27 0 gnd (bank 0) - gnd (bank 0) - 28 0 c6 c^6 f2 f^1 29 0 c5 c^5 f4 f^2 30 0 c4 c^4 f6 f^3 31 0 c2 c^2 f8 f^4 32 0 c1 c^1 f10 f^5 33 0 c0 c^0 f12 f^6 34 0 vcco (bank 0) - vcco (bank 0) - 35 - tck - tck - 36 - vcc - vcc - 37 - gnd - gnd - 38 - nc 2 -i 2 - 39 0 d14 d^14 g12 g^6 40 0 d13 d^13 g10 g^5 41 0 d12 d^12 g8 g^4 42 0 d10 d^10 g6 g^3 43 0 d9 d^9 g4 g^2 44 0 d8 d^8 g2 g^1 45 - nc 2 -i 2 - 46 0 gnd (bank 0) - gnd (bank 0) - 47 0 vcco (bank 0) - vcco (bank 0) - 48 0 d6 d^6 h12 h^6 49 0 d5 d^5 h10 h^5 50 0 d4 d^4 h8 h^4 51 0 d2 d^2 h6 h^3 52 0 d1 d^1 h4 h^2 53 0 d0 d^0 h2 h^1 54 0 clk1/i - clk1/i - 55 1 gnd (bank 1) - gnd (bank 1) - 56 1 clk2/i - clk2/i - ispmach 4128v and 4256v logic signal connections: 144-pin tqfp (cont.) pin number bank number ispmach 4128v ispmach 4256v glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 51 57 - vcc - vcc - 58 1 e0 e^0 i2 i^1 59 1 e1 e^1 i4 i^2 60 1 e2 e^2 i6 i^3 61 1 e4 e^4 i8 i^4 62 1 e5 e^5 i10 i^5 63 1 e6 e^6 i12 i^6 64 1 vcco (bank 1) - vcco (bank 1) - 65 1 gnd (bank 1) - gnd (bank 1) - 66 1 e8 e^8 j2 j^1 67 1 e9 e^9 j4 j^2 68 1 e10 e^10 j6 j^3 69 1 e12 e^12 j8 j^4 70 1 e13 e^13 j10 j^5 71 1 e14 e^14 j12 j^6 72 - nc 2 -i 2 - 73 - gnd - gnd - 74 - tms - tms - 75 1 vcco (bank 1) - vcco (bank 1) - 76 1 f0 f^0 k12 k^6 77 1 f1 f^1 k10 k^5 78 1 f2 f^2 k8 k^4 79 1 f4 f^4 k6 k^3 80 1 f5 f^5 k4 k^2 81 1 f6 f^6 k2 k^1 82 1 gnd (bank 1) - gnd (bank 1) - 83 1 f8 f^8 l14 l^7 84 1 f9 f^9 l12 l^6 85 1 f10 f^10 l10 l^5 86 1 f12 f^12 l8 l^4 87 1 f13 f^13 l6 l^3 88 1 f14 f^14 l4 l^2 89 - nc 2 -i 2 - 90 1 gnd (bank 1) 1 - nc 1 - 91 1 vcco (bank 1) - vcco (bank 1) - 92 - nc 2 -i 2 - 93 1 g14 g^14 m2 m^1 94 1 g13 g^13 m4 m^2 95 1 g12 g^12 m6 m^3 96 1 g10 g^10 m8 m^4 97 1 g9 g^9 m10 m^5 98 1 g8 g^8 m12 m^6 99 1 gnd (bank 1) - gnd (bank 1) - ispmach 4128v and 4256v logic signal connections: 144-pin tqfp (cont.) pin number bank number ispmach 4128v ispmach 4256v glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 52 100 1 g6 g^6 n2 n^1 101 1 g5 g^5 n4 n^2 102 1 g4 g^4 n6 n^3 103 1 g2 g^2 n8 n^4 104 1 g1 g^1 n10 n^5 105 1 g0 g^0 n12 n^6 106 1 vcco (bank 1) - vcco (bank 1) - 107 - tdo - tdo - 108 - vcc - vcc - 109 - gnd - gnd - 110 - nc 2 -i 2 - 111 1 h14 h^14 o12 o^6 112 1 h13 h^13 o10 o^5 113 1 h12 h^12 o8 o^4 114 1 h10 h^10 o6 o^3 115 1 h9 h^9 o4 o^2 116 1 h8 h^8 o2 o^1 117 - nc 2 -i 2 - 118 1 gnd (bank 1) - gnd (bank 1) - 119 1 vcco (bank 1) - vcco (bank 1) - 120 1 h6 h^6 p12 p^6 121 1 h5 h^5 p10 p^5 122 1 h4 h^4 p8 p^4 123 1 h2 h^2 p6 p^3 124 1 h1 h^1 p4 p^2 125 1 h0/goe1 h^0 p2/goe1 p^1 126 1 clk3/i - clk3/i - 127 0 gnd (bank 0) - gnd (bank 0) - 128 0 clk0/i - clk0/1 - 129 - vcc - vcc - 130 0 a0/goe0 a^0 a2/goe0 a^1 131 0 a1 a^1 a4 a^2 132 0 a2 a^2 a6 a^3 133 0 a4 a^4 a8 a^4 134 0 a5 a^5 a10 a^5 135 0 a6 a^6 a12 a^6 136 0 vcco (bank 0) - vcco (bank 0) - 137 0 gnd (bank 0) - gnd (bank 0) - 138 0 a8 a^8 b2 b^1 139 0 a9 a^9 b4 b^2 140 0 a10 a^10 b6 b^3 141 0 a12 a^12 b8 b^4 142 0 a13 a^13 b10 b^5 ispmach 4128v and 4256v logic signal connections: 144-pin tqfp (cont.) pin number bank number ispmach 4128v ispmach 4256v glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 53 143 0 a14 a^14 b12 b^6 144 - nc 2 -i 2 - 1. for device migration considerations, these nc pins are gnd pins for i/o banks in ispmach 4128v devices. 2. for device migration considerations, these nc pins are input signal pins in ispmach 4256v devices. ispmach 4256v/b/c, 4384v/b/c, 4512v/b/c, logic signal connections: 176-pin tqfp pin number bank number ispmach 4256v/b/c ispmach 4384v/b/c ispmach 4512v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp 1-nc-n c-nc - 2- gnd - gnd - gnd - 3- tdi - tdi - tdi - 4 0 vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - 50 c14 c^7 c14 c^7 c14 c^7 60 c12 c^6 c12 c^6 c12 c^6 70 c10 c^5 c10 c^5 c10 c^5 80c8 c^4 c8 c^4 c8 c^4 90c6 c^3 c6 c^3 c6 c^3 10 0 c4 c^2 c4 c^2 c4 c^2 11 0 c2 c^1 c2 c^1 c2 c^1 12 0 c0 c^0 c0 c^0 c0 c^0 13 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - 14 0 d14 d^7 e14 e^7 g14 g^7 15 0 d12 d^6 e12 e^6 g12 g^6 16 0 d10 d^5 e10 e^5 g10 g^5 17 0 d8 d^4 e8 e^4 g8 g^4 18 0 d6 d^3 e6 e^3 g6 g^3 19 0 d4 d^2 e4 e^2 g4 g^2 20 0 d2 d^1 e2 e^1 g2 g^1 21 0 d0 d^0 e0 e^0 g0 g^0 22 0 vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - 23 0 e0 e^0 h0 h^0 j0 j^0 24 0 e2 e^1 h2 h^1 j2 j^1 25 0 e4 e^2 h4 h^2 j4 j^2 26 0 e6 e^3 h6 h^3 j6 j^3 27 0 e8 e^4 h8 h^4 j8 j^4 28 0 e10 e^5 h10 h^5 j10 j^5 29 0 e12 e^6 h12 h^6 j12 j^6 30 0 e14 e^7 h14 h^7 j14 j^7 31 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - 32 0 f0 f^0 j0 j^0 n0 n^0 ispmach 4128v and 4256v logic signal connections: 144-pin tqfp (cont.) pin number bank number ispmach 4128v ispmach 4256v glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 54 33 0 f2 f^1 j2 j^1 n2 n^1 34 0 f4 f^2 j4 j^2 n4 n^2 35 0 f6 f^3 j6 j^3 n6 n^3 36 0 f8 f^4 j8 j^4 n8 n^4 37 0 f10 f^5 j10 j^5 n10 n^5 38 0 f12 f^6 j12 j^6 n12 n^6 39 0 f14 f^7 j14 j^7 n14 n^7 40 0 vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - 41 - tck - tck - tck - 42 - vcc - vcc - vcc - 43 - nc - n c-nc - 44 - nc - n c-nc - 45 - nc - n c-nc - 46 - gnd - gnd (bank 0) - gnd - 47 0 g14 g^7 k14 k^7 o14 o^7 48 0 g12 g^6 k12 k^6 o12 o^6 49 0 g10 g^5 k10 k^5 o10 o^5 50 0 g8 g^4 k8 k^4 o8 o^4 51 0 g6 g^3 k6 k^3 o6 o^3 52 0 g4 g^2 k4 k^2 o4 o^2 53 0 g2 g^1 k2 k^1 o2 o^1 54 0 g0 g^0 k0 k^0 o0 o^0 55 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - 56 0 vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - 57 0 h14 h^7 l14 l^7 p14 p^7 58 0 h12 h^6 l12 l^6 p12 p^6 59 0 h10 h^5 l10 l^5 p10 p^5 60 0 h8 h^4 l8 l^4 p8 p^4 61 0 h6 h^3 l6 l^3 p6 p^3 62 0 h4 h^2 l4 l^2 p4 p^2 63 0 h2 h^1 l2 l^1 p2 p^1 64 0 h0 h^0 l0 l^0 p0 p^0 65 - gnd - gnd - gnd - 66 0 clk1/i - clk1/i - clk1/i - 67 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - 68 1 clk2/i - clk2/i - clk2/i - 69 - vcc - vcc - vcc - 70 1 i0 i^0 m0 m^0 ax0 ax^0 71 1 i2 i^1 m2 m^1 ax2 ax^1 72 1 i4 i^2 m4 m^2 ax4 ax^2 73 1 i6 i^3 m6 m^3 ax6 ax^3 ispmach 4256v/b/c, 4384v/b/c, 4512v/b/c, logic signal connections: 176-pin tqfp (cont.) pin number bank number ispmach 4256v/b/c ispmach 4384v/b/c ispmach 4512v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 55 74 1 i8 i^4 m8 m^4 ax8 ax^4 75 1 i10 i^5 m10 m^5 ax10 ax^5 76 1 i12 i^6 m12 m^6 ax12 ax^6 77 1 i14 i^7 m14 m^7 ax14 ax^7 78 1 vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - 79 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - 80 1 j0 j^0 n0 n^0 bx0 bx^0 81 1 j2 j^1 n2 n^1 bx2 bx^1 82 1 j4 j^2 n4 n^2 bx4 bx^2 83 1 j6 j^3 n6 n^3 bx6 bx^3 84 1 j8 j^4 n8 n^4 bx8 bx^4 85 1 j10 j^5 n10 n^5 bx10 bx^5 86 1 j12 j^6 n12 n^6 bx12 bx^6 87 1 j14 j^7 n14 n^7 bx14 bx^7 88 - vcc - vcc - vcc - 89 - nc - n c-nc - 90 - gnd - gnd - gnd - 91 - tms - tms - tms - 92 1 vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - 93 1 k14 k^7 o14 o^7 cx14 cx^7 94 1 k12 k^6 o12 o^6 cx12 cx^6 95 1 k10 k^5 o10 o^5 cx10 cx^5 96 1 k8 k^4 o8 o^4 cx8 cx^4 97 1 k6 k^3 o6 o^3 cx6 cx^3 98 1 k4 k^2 o4 o^2 cx4 cx^2 99 1 k2 k^1 o2 o^1 cx2 cx^1 100 1 k0 k^0 o0 o^0 cx0 cx^0 101 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - 102 1 l14 l^7 ax14 ax^7 gx14 gx^7 103 1 l12 l^6 ax12 ax^6 gx12 gx^6 104 1 l10 l^5 ax10 ax^5 gx10 gx^5 105 1 l8 l^4 ax8 ax^4 gx8 gx^4 106 1 l6 l^3 ax6 ax^3 gx6 gx^3 107 1 l4 l^2 ax4 ax^2 gx4 gx^2 108 1 l2 l^1 ax2 ax^1 gx2 gx^1 109 1 l0 l^0 ax0 ax^0 gx0 gx^0 110 1 vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - 111 1 m0 m^0 dx0 dx^0 jx0 jx^0 112 1 m2 m^1 dx2 dx^1 jx2 jx^1 113 1 m4 m^2 dx4 dx^2 jx4 jx^2 114 1 m6 m^3 dx6 dx^3 jx6 jx^3 ispmach 4256v/b/c, 4384v/b/c, 4512v/b/c, logic signal connections: 176-pin tqfp (cont.) pin number bank number ispmach 4256v/b/c ispmach 4384v/b/c ispmach 4512v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 56 115 1 m8 m^4 dx8 dx^4 jx8 jx^4 116 1 m10 m^5 dx10 dx^5 jx10 jx^5 117 1 m12 m^6 dx12 dx^6 jx12 jx^6 118 1 m14 m^7 dx14 dx^7 jx14 jx^7 119 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - 120 1 n0 n^0 fx0 fx^0 nx0 nx^0 121 1 n2 n^1 fx2 fx^1 nx2 nx^1 122 1 n4 n^2 fx4 fx^2 nx4 nx^2 123 1 n6 n^3 fx6 fx^3 nx6 nx^3 124 1 n8 n^4 fx8 fx^4 nx8 nx^4 125 1 n10 n^5 fx10 fx^5 nx10 nx^5 126 1 n12 n^6 fx12 fx^6 nx12 nx^6 127 1 n14 n^7 fx14 fx^7 nx14 nx^7 128 1 vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - 129 - tdo - tdo - tdo - 130 - vcc - vcc - vcc - 131 - nc - n c-nc - 132 - nc - n c-nc - 133 - nc - n c-nc - 134 - gnd - gnd - gnd - 135 1 o14 o^7 gx14 gx^7 ox14 ox^7 136 1 o12 o^6 gx12 gx^6 ox12 ox^6 137 1 o10 o^5 gx10 gx^5 ox10 ox^5 138 1 o8 o^4 gx8 gx^4 ox8 ox^4 139 1 o6 o^3 gx6 gx^3 ox6 ox^3 140 1 o4 o^2 gx4 gx^2 ox4 ox^2 141 1 o2 o^1 gx2 gx^1 ox2 ox^1 142 1 o0 o^0 gx0 gx^0 ox0 ox^0 143 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - 144 1 vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - 145 1 p14 p^7 hx14 hx^7 px14 px^7 146 1 p12 p^6 hx12 hx^6 px12 px^6 147 1 p10 p^5 hx10 hx^5 px10 px^5 148 1 p8 p^4 hx8 hx^4 px8 px^4 149 1 p6 p^3 hx6 hx^3 px6 px^3 150 1 p4 p^2 hx4 hx^2 px4 px^2 151 1 p2/goe1 p^1 hx2/goe1 hx^1 px2/goe1 px^1 152 1 p0 p^0 hx0 hx^0 px0 px^0 153 - gnd - gnd - gnd - 154 1 clk3/i - clk3/i - clk3/i - 155 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - ispmach 4256v/b/c, 4384v/b/c, 4512v/b/c, logic signal connections: 176-pin tqfp (cont.) pin number bank number ispmach 4256v/b/c ispmach 4384v/b/c ispmach 4512v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 57 156 0 clk0/i - clk0/i - clk0/i - 157 - vcc - vcc - vcc - 158 0 a0 a^0 a0 a^0 a0 a^0 159 0 a2/goe0 a^1 a2/goe0 a^1 a2//goe0 a^1 160 0 a4 a^2 a4 a^2 a4 a^2 161 0 a6 a^3 a6 a^3 a6 a^3 162 0 a8 a^4 a8 a^4 a8 a^4 163 0 a10 a^5 a10 a^5 a10 a^5 164 0 a12 a^6 a12 a^6 a12 a^6 165 0 a14 a^7 a14 a^7 a14 a^7 166 0 vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - 167 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - 168 0 b0 b^0 b0 b^0 b0 b^0 169 0 b2 b^1 b2 b^1 b2 b^1 170 0 b4 b^2 b4 b^2 b4 b^2 171 0 b6 b^3 b6 b^3 b6 b^3 172 0 b8 b^4 b8 b^4 b8 b^4 173 0 b10 b^5 b10 b^5 b10 b^5 174 0 b12 b^6 b12 b^6 b12 b^6 175 0 b14 b^7 b14 b^7 b14 b^7 176 - vcc - vcc - vcc - ispmach 4256v/b/c, 4384v/b/c, 4512v/b/c logic signal connections: 256-ball fpbga ball number i/o bank ispmach 4256v/b/c 128-i/o ispmach 4256v/b/c 160-i/o ispmach 4384v/b/c ispmach 4512v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp -- ----vcc-vcc- -- gnd - gnd - gnd - gnd - c3 - tdi - tdi - tdi - tdi - - 0 vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - b1 0 c14 c^7 c9 c^9 c14 c^7 c14 c^7 f5 0 c12 c^6 c8 c^8 c12 c^6 c12 c^6 d3 0 c10 c^5 c7 c^7 c10 c^5 c10 c^5 c1 0 c8 c^4 c6 c^6 c8 c^4 c8 c^4 c2 0 c6 c^3 c5 c^5 c6 c^3 c6 c^3 e3 0 c4 c^2 c4 c^4 c4 c^2 c4 c^2 d2 0 c2 c^1 c3 c^3 c2 c^1 c2 c^1 f6 0 c0 c^0 c2 c^2 c0 c^0 c0 c^0 d1 0 nc - c1 c^1 f6 f^3 h0 h^0 ispmach 4256v/b/c, 4384v/b/c, 4512v/b/c, logic signal connections: 176-pin tqfp (cont.) pin number bank number ispmach 4256v/b/c ispmach 4384v/b/c ispmach 4512v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 58 e2 0 nc - c0 c^0 f4 f^2 h4 h^2 e4 0 nc - nc - d6 d^3 f4 f^2 g5 0 nc - nc - d4 d^2 f6 f^3 e1 0 n c-nc-nc- f8f^4 - 0 - - vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - - 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - f2 0 n c-nc-nc-f10f^5 f1 0 nc - nc - d2 d^1 f12 f^6 g1 0 nc - nc - d0 d^0 f14 f^7 g6 0 nc - d9 d^9 f2 f^1 h8 h^4 g4 0 nc - d8 d^8 f0 f^0 h12 h^6 h6 0 d14 d^7 d7 d^7 e14 e^7 g14 g^7 g3 0 d12 d^6 d6 d^6 e12 e^6 g12 g^6 h5 0 d10 d^5 d5 d^5 e10 e^5 g10 g^5 g2 0 d8 d^4 d4 d^4 e8 e^4 g8 g^4 h1 0 d6 d^3 d3 d^3 e6 e^3 g6 g^3 h2 0 d4 d^2 d2 d^2 e4 e^2 g4 g^2 h3 0 d2 d^1 d1 d^1 e2 e^1 g2 g^1 h4 0 d0 d^0 d0 d^0 e0 e^0 g0 g^0 - 0 vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - - 0 - - gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - j4 0 e0 e^0 e0 e^0 h0 h^0 j0 j^0 j3 0 e2 e^1 e1 e^1 h2 h^1 j2 j^1 j2 0 e4 e^2 e2 e^2 h4 h^2 j4 j^2 j1 0 e6 e^3 e3 e^3 h6 h^3 j6 j^3 k1 0 e8 e^4 e4 e^4 h8 h^4 j8 j^4 j5 0 e10 e^5 e5 e^5 h10 h^5 j10 j^5 k2 0 e12 e^6 e6 e^6 h12 h^6 j12 j^6 j6 0 e14 e^7 e7 e^7 h14 h^7 j14 j^7 k3 0 nc - e8 e^8 g0 g^0 i0 i^0 k4 0 nc - e9 e^9 g2 g^1 i4 i^2 l1 0 nc - nc - i14 i^7 k0 k^0 l2 0 nc - nc - i12 i^6 k2 k^1 m1 0 n c-nc-nc- k4k^2 - 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - - 0 - - vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - m2 0 n c-nc-nc- k6k^3 n1 0 nc - nc - i10 i^5 k8 k^4 m3 0 nc - nc - i8 i^4 k10 k^5 m4 0 nc - f0 f^0 g4 g^2 i8 i^4 n2 0 nc - f1 f^1 g6 g^3 i12 i^6 ispmach 4256v/b/c, 4384v/b/c, 4512v/b/c logic signal connections: 256-ball fpbga (cont.) ball number i/o bank ispmach 4256v/b/c 128-i/o ispmach 4256v/b/c 160-i/o ispmach 4384v/b/c ispmach 4512v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 59 k5 0 f0 f^0 f2 f^2 j0 j^0 n0 n^0 p1 0 f2 f^1 f3 f^3 j2 j^1 n2 n^1 k6 0 f4 f^2 f4 f^4 j4 j^2 n4 n^2 n3 0 f6 f^3 f5 f^5 j6 j^3 n6 n^3 l5 0 f8 f^4 f6 f^6 j8 j^4 n8 n^4 p2 0 f10 f^5 f7 f^7 j10 j^5 n10 n^5 l6 0 f12 f^6 f8 f^8 j12 j^6 n12 n^6 r1 0 f14 f^7 f9 f^9 j14 j^7 n14 n^7 - 0 vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - p3 - tck - tck - tck - tck - -- vcc - vcc - vcc - vcc - -- gnd - gnd - gnd - gnd - - 0 - - gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - t2 0 nc - g9 g^9 i6 i^3 k12 k^6 m5 0 nc - g8 g^8 i4 i^2 k14 k^7 n4 0 g14 g^7 g7 g^7 k14 k^7 o14 o^7 t3 0 g12 g^6 g6 g^6 k12 k^6 o12 o^6 r3 0 g10 g^5 g5 g^5 k10 k^5 o10 o^5 m6 0 g8 g^4 g4 g^4 k8 k^4 o8 o^4 p4 0 g6 g^3 g3 g^3 k6 k^3 o6 o^3 l7 0 g4 g^2 g2 g^2 k4 k^2 o4 o^2 n5 0 g2 g^1 g1 g^1 k2 k^1 o2 o^1 m7 0 g0 g^0 g0 g^0 k0 k^0 o0 o^0 p5 0 nc - nc - g8 g^4 m0 m^0 r4 0 nc - nc - g10 g^5 m4 m^2 t4 0 n c-nc-nc- l0l^0 - 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - - 0 vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - r5 0 n c-nc-nc- l4l^2 t5 0 nc - nc - i2 i^1 l8 l^4 r6 0 nc - nc - i0 i^0 l12 l^6 t6 0 nc - h9 h^9 g12 g^6 m8 m^4 n7 0 nc - h8 h^8 g14 g^7 m12 m^6 p7 0 h14 h^7 h7 h^7 l14 l^7 p14 p^7 r7 0 h12 h^6 h6 h^6 l12 l^6 p12 p^6 l8 0 h10 h^5 h5 h^5 l10 l^5 p10 p^5 t7 0 h8 h^4 h4 h^4 l8 l^4 p8 p^4 m8 0 h6 h^3 h3 h^3 l6 l^3 p6 p^3 n8 0 h4 h^2 h2 h^2 l4 l^2 p4 p^2 r8 0 h2 h^1 h1 h^1 l2 l^1 p2 p^1 p8 0 h0 h^0 h0 h^0 l0 l^0 p0 p^0 ispmach 4256v/b/c, 4384v/b/c, 4512v/b/c logic signal connections: 256-ball fpbga (cont.) ball number i/o bank ispmach 4256v/b/c 128-i/o ispmach 4256v/b/c 160-i/o ispmach 4384v/b/c ispmach 4512v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 60 -- gnd- gnd - gnd - gnd - t8 0 clk1/i - clk1/i - clk1/i - clk1/i - - 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - n9 1 clk2/i - clk2/i - clk2/i - clk2/i - -- vcc - vcc - vcc - vcc - p9 1 i0 i^0 i0 i^0 m0 m^0 ax0 ax^0 r9 1 i2 i^1 i1 i^1 m2 m^1 ax2 ax^1 t9 1 i4 i^2 i2 i^2 m4 m^2 ax4 ax^2 t10 1 i6 i^3 i3 i^3 m6 m^3 ax6 ax^3 r10 1 i8 i^4 i4 i^4 m8 m^4 ax8 ax^4 m9 1 i10 i^5 i5 i^5 m10 m^5 ax10 ax^5 p10 1 i12 i^6 i6 i^6 m12 m^6 ax12 ax^6 l9 1 i14 i^7 i7 i^7 m14 m^7 ax14 ax^7 n10 1 nc - i8 i^8 bx14 bx^7 dx0 dx^0 t11 1 nc - i9 i^9 bx12 bx^6 dx4 dx^2 r11 1 nc - nc - p0 p^0 ex0 ex^0 t12 1 nc - nc - p2 p^1 ex4 ex^2 n12 1 nc - nc - nc - ex8 ex^4 - 1 vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - - 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - r12 1 nc - nc - nc - ex12 ex^6 t13 1 nc - j0 j^0 bx10 bx^5 dx8 dx^4 p12 1 nc - j1 j^1 bx8 bx^4 dx12 dx^6 m10 1 j0 j^0 j2 j^2 n0 n^0 bx0 bx^0 r13 1 j2 j^1 j3 j^3 n2 n^1 bx2 bx^1 l10 1 j4 j^2 j4 j^4 n4 n^2 bx4 bx^2 t14 1 j6 j^3 j5 j^5 n6 n^3 bx6 bx^3 m11 1 j8 j^4 j6 j^6 n8 n^4 bx8 bx^4 r14 1 j10 j^5 j7 j^7 n10 n^5 bx10 bx^5 p13 1 j12 j^6 j8 j^8 n12 n^6 bx12 bx^6 n13 1 j14 j^7 j9 j^9 n14 n^7 bx14 bx^7 m12 1 nc - nc - p4 p^2 fx0 fx^0 t15 1 nc - nc - p6 p^3 fx2 fx^1 -- vcc - vcc - vcc - vcc - -- gnd- gnd - gnd - gnd - - 1 - - gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - p14 - tms - tms - tms - tms - - 1 vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - l12 1 nc - nc - nc - fx4 fx^2 r16 1 nc - nc - p8 p^4 fx6 fx^3 n14 1 nc - nc - p10 p^5 fx8 fx^4 ispmach 4256v/b/c, 4384v/b/c, 4512v/b/c logic signal connections: 256-ball fpbga (cont.) ball number i/o bank ispmach 4256v/b/c 128-i/o ispmach 4256v/b/c 160-i/o ispmach 4384v/b/c ispmach 4512v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 61 p15 1 k14 k^7 k9 k^9 o14 o^7 cx14 cx^7 l11 1 k12 k^6 k8 k^8 o12 o^6 cx12 cx^6 p16 1 k10 k^5 k7 k^7 o10 o^5 cx10 cx^5 k11 1 k8 k^4 k6 k^6 o8 o^4 cx8 cx^4 m14 1 k6 k^3 k5 k^5 o6 o^3 cx6 cx^3 k12 1 k4 k^2 k4 k^4 o4 o^2 cx4 cx^2 n15 1 k2 k^1 k3 k^3 o2 o^1 cx2 cx^1 n16 1 k0 k^0 k2 k^2 o0 o^0 cx0 cx^0 m15 1 nc - k1 k^1 bx6 bx^3 hx0 hx^0 m13 1 nc - k0 k^0 bx4 bx^2 hx4 hx^2 - 1 - - vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - - 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - m16 1 nc - nc - nc - fx10 fx^5 l15 1 nc - nc - p12 p^6 fx12 fx^6 l16 1 nc - nc - p14 p^7 fx14 fx^7 j11 1 nc - l9 l^9 bx2 bx^1 hx8 hx^4 k15 1 nc - l8 l^8 bx0 bx^0 hx12 hx^6 j12 1 l14 l^7 l7 l^7 ax14 ax^7 gx14 gx^7 k13 1 l12 l^6 l6 l^6 ax12 ax^6 gx12 gx^6 k14 1 l10 l^5 l5 l^5 ax10 ax^5 gx10 gx^5 k16 1 l8 l^4 l4 l^4 ax8 ax^4 gx8 gx^4 j16 1 l6 l^3 l3 l^3 ax6 ax^3 gx6 gx^3 j15 1 l4 l^2 l2 l^2 ax4 ax^2 gx4 gx^2 h16 1 l2 l^1 l1 l^1 ax2 ax^1 gx2 gx^1 j13 1 l0 l^0 l0 l^0 ax0 ax^0 gx0 gx^0 - 1 vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - - 1 - - gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - j14 1 m0 m^0 m0 m^0 dx0 dx^0 jx0 jx^0 h15 1 m2 m^1 m1 m^1 dx2 dx^1 jx2 jx^1 h14 1 m4 m^2 m2 m^2 dx4 dx^2 jx4 jx^2 h13 1 m6 m^3 m3 m^3 dx6 dx^3 jx6 jx^3 g16 1 m8 m^4 m4 m^4 dx8 dx^4 jx8 jx^4 h12 1 m10 m^5 m5 m^5 dx10 dx^5 jx10 jx^5 g15 1 m12 m^6 m6 m^6 dx12 dx^6 jx12 jx^6 h11 1 m14 m^7 m7 m^7 dx14 dx^7 jx14 jx^7 f16 1 nc - m8 m^8 cx0 cx^0 ix0 ix^0 g13 1 nc - m9 m^9 cx2 cx^1 ix4 ix^2 g14 1 nc - nc - ex14 ex^7 kx0 kx^0 f15 1 nc - nc - ex12 ex^6 kx2 kx^1 e16 1 nc - nc - nc - kx4 kx^2 - 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - ispmach 4256v/b/c, 4384v/b/c, 4512v/b/c logic signal connections: 256-ball fpbga (cont.) ball number i/o bank ispmach 4256v/b/c 128-i/o ispmach 4256v/b/c 160-i/o ispmach 4384v/b/c ispmach 4512v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 62 - 1 - - vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - e15 1 nc - nc - nc - kx6 kx^3 g12 1 nc - nc - ex10 ex^5 kx8 kx^4 e13 1 nc - nc - ex8 ex^4 kx10 kx^5 d16 1 nc - n0 n^0 cx4 cx^2 ix8 ix^4 e14 1 nc - n1 n^1 cx6 cx^3 ix12 ix^6 g11 1 n0 n^0 n2 n^2 fx0 fx^0 nx0 nx^0 d15 1 n2 n^1 n3 n^3 fx2 fx^1 nx2 nx^1 f11 1 n4 n^2 n4 n^4 fx4 fx^2 nx4 nx^2 c16 1 n6 n^3 n5 n^5 fx6 fx^3 nx6 nx^3 f12 1 n8 n^4 n6 n^6 fx8 fx^4 nx8 nx^4 d14 1 n10 n^5 n7 n^7 fx10 fx^5 nx10 nx^5 c15 1 n12 n^6 n8 n^8 fx12 fx^6 nx12 nx^6 b16 1 n14 n^7 n9 n^9 fx14 fx^7 nx14 nx^7 - 1 vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - c14 - tdo - tdo - tdo - tdo - -- vcc - vcc - vcc - vcc - -- gnd - gnd - gnd - gnd - - 1 - - gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - a15 1 nc - nc - ex6 ex^3 kx12 kx^6 b14 1 nc - nc - ex4 ex^2 kx14 kx^7 e12 1 o14 o^7 o9 o^9 gx14 gx^7 ox14 ox^7 a14 1 o12 o^6 o8 o^8 gx12 gx^6 ox12 ox^6 c13 1 o10 o^5 o7 o^7 gx10 gx^5 ox10 ox^5 d13 1 o8 o^4 o6 o^6 gx8 gx^4 ox8 ox^4 e11 1 o6 o^3 o5 o^5 gx6 gx^3 ox6 ox^3 b13 1 o4 o^2 o4 o^4 gx4 gx^2 ox4 ox^2 f10 1 o2 o^1 o3 o^3 gx2 gx^1 ox2 ox^1 c12 1 o0 o^0 o2 o^2 gx0 gx^0 ox0 ox^0 e10 1 nc - o1 o^1 cx8 cx^4 mx0 mx^0 a13 1 nc - o0 o^0 cx10 cx^5 mx4 mx^2 d12 1 nc - nc - nc - lx0 lx^0 - 1 gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - gnd (bank 1) - - 1 vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - vcco (bank 1) - b12 1 nc - nc - nc - lx4 lx^2 a12 1 nc - nc - ex2 ex^1 lx8 lx^4 b11 1 nc - nc - ex0 ex^0 lx12 lx^6 a11 1 nc - p9 p^9 cx12 cx^6 mx8 mx^4 d10 1 nc - p8 p^8 cx14 cx^7 mx12 mx^6 c10 1 p14 p^7 p7 p^7 hx14 hx^7 px14 px^7 b10 1 p12 p^6 p6 p6 hx12 hx^6 px12 px^6 ispmach 4256v/b/c, 4384v/b/c, 4512v/b/c logic signal connections: 256-ball fpbga (cont.) ball number i/o bank ispmach 4256v/b/c 128-i/o ispmach 4256v/b/c 160-i/o ispmach 4384v/b/c ispmach 4512v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 63 a10 1 p10 p^5 p5 p^5 hx10 hx^5 px10 px^5 a9 1 p8 p^4 p4 p^4 hx8 hx^4 px8 px^4 f9 1 p6 p^3 p3 p^3 hx6 hx^3 px6 px^3 b9 1 p4 p^2 p2 p^2 hx4 hx^2 px4 px^2 e9 1 p2/goe1 p^1 p1/goe1 p^1 hx2/goe1 hx^1 px2/goe1 px^1 c9 1 p0 p^0 p0 p^0 hx0 hx^0 px0 px^0 -- gnd- gnd gnd - gnd - d9 1 clk3/i - clk3/i - clk3/i - clk3/i - - 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - b8 0 clk0/i - clk0/i - clk0/i - clk0/i - -- vcc - vcc - vcc - vcc - d8 0 a0 a^0 a0 a^0 a0 a^0 a0 a^0 c8 0 a2/goe0 a^1 a1/goe0 a^1 a2/goe0 a^1 a2/goe0 a^1 a8 0 a4 a^2 a2 a^2 a4 a^2 a4 a^2 a7 0 a6 a^3 a3 a^3 a6 a^3 a6 a^3 b7 0 a8 a^4 a4 a^4 a8 a^4 a8 a^4 e8 0 a10 a^5 a5 a^5 a10 a^5 a10 a^5 d7 0 a12 a^6 a6 a^6 a12 a^6 a12 a^6 f8 0 a14 a^7 a7 a^7 a14 a^7 a14 a^7 c7 0 nc - a8 a^8 f14 f^7 d0 d^0 a6 0 nc - a9 a^9 f12 f^6 d4 d^2 b6 0 nc - nc - d14 d^7 e0 e^0 a5 0 nc - nc - d12 d^6 e4 e^2 b5 0 n c-nc-nc- e8e^4 - 0 vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - vcco (bank 0) - - 0 gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - gnd (bank 0) - d5 0 n c-nc-nc-e12e^6 a4 0 nc - b0 b^0 f10 f^5 d8 d^4 e7 0 nc - b1 b^1 f8 f^4 d12 d^6 a3 0 b0 b^0 b2 b^2 b0 b^0 b0 b^0 f7 0 b2 b^1 b3 b^3 b2 b^1 b2 b^1 b4 0 b4 b^2 b4 b^4 b4 b^2 b4 b^2 c5 0 b6 b^3 b5 b^5 b6 b^3 b6 b^3 a2 0 b8 b^4 b6 b^6 b8 b^4 b8 b^4 e6 0 b10 b^5 b7 b^7 b10 b^5 b10 b^5 b3 0 b12 b^6 b8 b^8 b12 b^6 b12 b^6 c4 0 b14 b^7 b9 b^9 b14 b^7 b14 b^7 d4 0 nc - nc - d10 d^5 f0 f^0 e5 0 nc - nc - d8 d^4 f2 f^1 -- vcc - vcc - vcc - vcc - -- ----gnd-gnd- ispmach 4256v/b/c, 4384v/b/c, 4512v/b/c logic signal connections: 256-ball fpbga (cont.) ball number i/o bank ispmach 4256v/b/c 128-i/o ispmach 4256v/b/c 160-i/o ispmach 4384v/b/c ispmach 4512v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 64 - 0 - - - - gnd (bank 0) - gnd (bank 0) - note: vcc, vcco and gnd are tied together to their respective common signal on the package substrate. see power supply and nc c on- nections table for vcc/ vcco/gnd pin de nitions. ispmach 4256v/b/c, 4384v/b/c, 4512v/b/c logic signal connections: 256-ball fpbga (cont.) ball number i/o bank ispmach 4256v/b/c 128-i/o ispmach 4256v/b/c 160-i/o ispmach 4384v/b/c ispmach 4512v/b/c glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp glb/mc/pad orp
lattice semiconductor ispmach 4000v/b/c/z family data sheet 65 pa rt number description ordering information note: ispmach 4000 devices are all dual marked except the slowest commercial speed grade ispmach 4000z devices. for example, the commercial speed grade lc4128c-5t100c is also marked with the industrial grade -75i. the commercial grade is always one speed grade faster than the associated dual mark industrial grade. the slow- est commercial speed grade ispmach 4000z devices are marked as commercial grade only. ispmach 4000c (1.8v) commercial devices 1 device part number macrocells voltage t pd pa ck ag e pin/ball count i/o grade lc4032c lc4032c-25t48c 32 1.8 2.5 tqfp 48 32 c lc4032c-5t48c 32 1.8 5 tqfp 48 32 c lc4032c-75t48c 32 1.8 7.5 tqfp 48 32 c lc4032c-25t44c 32 1.8 2.5 tqfp 44 30 c lc4032c-5t44c 32 1.8 5 tqfp 44 30 c lc4032c-75t44c 32 1.8 7.5 tqfp 44 30 c device number 4032 = 32 macrocells 4064 = 64 macrocells 4128 = 128 macrocells 4256 = 256 macrocells 4384 = 384 macrocells 4512 = 512 macrocells lc xxxx x x ? xx x xxx x x xx production status blank = final production es = engineering samples i/o designator (if applicable) a = 128 i/os b = 160 i/os supply voltage v = 3.3v b = 2.5v c = 1.8v power z = zero power blank = low power speed 25 = 2.5ns 27 = 2.7ns 3 = 3.0ns 35 = 3.5ns 4 = 4.0ns 45 = 4.5ns 5 = 5.0ns 75 = 7.5ns 10 = 10.0ns pin/ball count 44 (1.0mm thickness) 48 (1.0mm thickness) 56 100 128 132 144 176 256 package t = tqfp f = fpbga m = csbga grade c = commercial i = industrial e = automotive device family
lattice semiconductor ispmach 4000v/b/c/z family data sheet 66 lc4064c lc4064c-25t100c 64 1.8 2.5 tqfp 100 64 c lc4064c-5t100c 64 1.8 5 tqfp 100 64 c lc4064c-75t100c 64 1.8 7.5 tqfp 100 64 c lc4064c-25t48c 64 1.8 2.5 tqfp 48 32 c lc4064c-5t48c 64 1.8 5 tqfp 48 32 c lc4064c-75t48c 64 1.8 7.5 tqfp 48 32 c lc4064c-25t44c 64 1.8 2.5 tqfp 44 30 c lc4064c-5t44c 64 1.8 5 tqfp 44 30 c lc4064c-75t44c 64 1.8 7.5 tqfp 44 30 c lc4128c lc4128c-27t128c 128 1.8 2.7 tqfp 128 92 c lc4128c-5t128c 128 1.8 5 tqfp 128 92 c lc4128c-75t128c 128 1.8 7.5 tqfp 128 92 c lc4128c-27t100c 128 1.8 2.7 tqfp 100 64 c lc4128c-5t100c 128 1.8 5 tqfp 100 64 c lc4128c-75t100c 128 1.8 7.5 tqfp 100 64 c lc4256c lc4256c-3f256ac 256 1.8 3 fpbga 256 128 c lc4256c-5f256ac 256 1.8 5 fpbga 256 128 c lc4256c-75f256ac 256 1.8 7.5 fpbga 256 128 c lc4256c-3f256bc 256 1.8 3 fpbga 256 160 c lc4256c-5f256bc 256 1.8 5 fpbga 256 160 c lc4256c-75f256bc 256 1.8 7.5 fpbga 256 160 c lc4256c-3t176c 256 1.8 3 tqfp 176 128 c lc4256c-5t176c 256 1.8 5 tqfp 176 128 c lc4256c-75t176c 256 1.8 7.5 tqfp 176 128 c lc4256c-3t100c 256 1.8 3 tqfp 100 64 c lc4256c-5t100c 256 1.8 5 tqfp 100 64 c lc4256c-75t100c 256 1.8 7.5 tqfp 100 64 c lc4384c lc4384c-35f256c 384 1.8 3.5 fpbga 256 192 c lc4384c-5f256c 384 1.8 5 fpbga 256 192 c lc4384c-75f256c 384 1.8 7.5 fpbga 256 192 c lc4384c-35t176c 384 1.8 3.5 tqfp 176 128 c lc4384c-5t176c 384 1.8 5 tqfp 176 128 c lc4384c-75t176c 384 1.8 7.5 tqfp 176 128 c lc4512c lc4512c-35f256c 512 1.8 3.5 fpbga 256 208 c lc4512c-5f256c 512 1.8 5 fpbga 256 208 c lc4512c-75f256c 512 1.8 7.5 fpbga 256 208 c lc4512c-35t176c 512 1.8 3.5 tqfp 176 128 c lc4512c-5t176c 512 1.8 5 tqfp 176 128 c lc4512c-75t176c 512 1.8 7.5 tqfp 176 128 c ispmach 4000c (1.8v) commercial devices 1 (cont.) device part number macrocells voltage t pd pa ck ag e pin/ball count i/o grade
lattice semiconductor ispmach 4000v/b/c/z family data sheet 67 ispmach 4000b (2.5v) commercial devices device part number macrocells voltage t pd pa ck ag e pin/ball count i/o grade lc4032b lc4032b-25t48c 32 2.5 2.5 tqfp 48 32 c lc4032b-5t48c 32 2.5 5 tqfp 48 32 c lc4032b-75t48c 32 2.5 7.5 tqfp 48 32 c lc4032b-25t44c 32 2.5 2.5 tqfp 44 30 c lc4032b-5t44c 32 2.5 5 tqfp 44 30 c lc4032b-75t44c 32 2.5 7.5 tqfp 44 30 c lc4064b lc4064b-25t100c 64 2.5 2.5 tqfp 100 64 c lc4064b-5t100c 64 2.5 5 tqfp 100 64 c lc4064b-75t100c 64 2.5 7.5 tqfp 100 64 c lc4064b-25t48c 64 2.5 2.5 tqfp 48 32 c lc4064b-5t48c 64 2.5 5 tqfp 48 32 c lc4064b-75t48c 64 2.5 7.5 tqfp 48 32 c lc4064b-25t44c 64 2.5 2.5 tqfp 44 30 c lc4064b-5t44c 64 2.5 5 tqfp 44 30 c lc4064b-75t44c 64 2.5 7.5 tqfp 44 30 c lc4128b lc4128b-27t128c 128 2.5 2.7 tqfp 128 92 c lc4128b-5t128c 128 2.5 5 tqfp 128 92 c lc4128b-75t128c 128 2.5 7.5 tqfp 128 92 c lc4128b-27t100c 128 2.5 2.7 tqfp 100 64 c lc4128b-5t100c 128 2.5 5 tqfp 100 64 c lc4128b-75t100c 128 2.5 7.5 tqfp 100 64 c lc4256b lc4256b-3f256ac 256 2.5 3 fpbga 256 128 c lc4256b-5f256ac 256 2.5 5 fpbga 256 128 c lc4256b-75f256ac 256 2.5 7.5 fpbga 256 128 c lc4256b-3f256bc 256 2.5 3 fpbga 256 160 c lc4256b-5f256bc 256 2.5 5 fpbga 256 160 c lc4256b-75f256bc 256 2.5 7.5 fpbga 256 160 c lc4256b-3t176c 256 2.5 3 tqfp 176 128 c lc4256b-5t176c 256 2.5 5 tqfp 176 128 c lc4256b-75t176c 256 2.5 7.5 tqfp 176 128 c lc4256b-3t100c 256 2.5 3 tqfp 100 64 c lc4256b-5t100c 256 2.5 5 tqfp 100 64 c lc4256b-75t100c 256 2.5 7.5 tqfp 100 64 c lc4384b lc4384b-35f256c 384 2.5 3.5 fpbga 256 192 c lc4384b-5f256c 384 2.5 5 fpbga 256 192 c lc4384b-75f256c 384 2.5 7.5 fpbga 256 192 c lc4384b-35t176c 384 2.5 3.5 tqfp 176 128 c lc4384b-5t176c 384 2.5 5 tqfp 176 128 c lc4384b-75t176c 384 2.5 7.5 tqfp 176 128 c
lattice semiconductor ispmach 4000v/b/c/z family data sheet 68 lc4512b lc4512b-35f256c 512 2.5 3.5 fpbga 256 208 c lc4512b-5f256c 512 2.5 5 fpbga 256 208 c lc4512b-75f256c 512 2.5 7.5 fpbga 256 208 c lc4512b-35t176c 512 2.5 3.5 tqfp 176 128 c lc4512b-5t176c 512 2.5 5 tqfp 176 128 c lc4512b-75t176c 512 2.5 7.5 tqfp 176 128 c ispmach 4000v (3.3v) commercial devices device part number macrocells voltage t pd pa ck ag e pin/ball count i/o grade lc4032v lc4032v-25t48c 32 3.3 2.5 tqfp 48 32 c lc4032v-5t48c 32 3.3 5 tqfp 48 32 c lc4032v-75t48c 32 3.3 7.5 tqfp 48 32 c lc4032v-25t44c 32 3.3 2.5 tqfp 44 30 c lc4032v-5t44c 32 3.3 5 tqfp 44 30 c lc4032v-75t44c 32 3.3 7.5 tqfp 44 30 c lc4064v lc4064v-25t100c 64 3.3 2.5 tqfp 100 64 c lc4064v-5t100c 64 3.3 5 tqfp 100 64 c lc4064v-75t100c 64 3.3 7.5 tqfp 100 64 c lc4064v-25t48c 64 3.3 2.5 tqfp 48 32 c lc4064v-5t48c 64 3.3 5 tqfp 48 32 c lc4064v-75t48c 64 3.3 7.5 tqfp 48 32 c lc4064v-25t44c 64 3.3 2.5 tqfp 44 30 c lc4064v-5t44c 64 3.3 5 tqfp 44 30 c lc4064v-75t44c 64 3.3 7.5 tqfp 44 30 c lc4128v lc4128v-27t144c 128 3.3 2.7 tqfp 144 96 c lc4128v-5t144c 128 3.3 5 tqfp 144 96 c lc4128v-75t144c 128 3.3 7.5 tqfp 144 96 c lc4128v-27t128c 128 3.3 2.7 tqfp 128 92 c lc4128v-5t128c 128 3.3 5 tqfp 128 92 c lc4128v-75t128c 128 3.3 7.5 tqfp 128 92 c lc4128v-27t100c 128 3.3 2.7 tqfp 100 64 c lc4128v-5t100c 128 3.3 5 tqfp 100 64 c lc4128v-75t100c 128 3.3 7.5 tqfp 100 64 c ispmach 4000b (2.5v) commercial devices (cont.) device part number macrocells voltage t pd pa ck ag e pin/ball count i/o grade
lattice semiconductor ispmach 4000v/b/c/z family data sheet 69 lc4256v lc4256v-3f256ac 256 3.3 3 fpbga 256 128 c lc4256v-5f256ac 256 3.3 5 fpbga 256 128 c lc4256v-75f256ac 256 3.3 7.5 fpbga 256 128 c lc4256v-3f256bc 256 3.3 3 fpbga 256 160 c lc4256v-5f256bc 256 3.3 5 fpbga 256 160 c lc4256v-75f256bc 256 3.3 7.5 fpbga 256 160 c lc4256v-3t176c 256 3.3 3 tqfp 176 128 c lc4256v-5t176c 256 3.3 5 tqfp 176 128 c lc4256v-75t176c 256 3.3 7.5 tqfp 176 128 c lc4256v-3t144c 256 3.3 3 tqfp 144 96 c lc4256v-5t144c 256 3.3 5 tqfp 144 96 c lc4256v-75t144c 256 3.3 7.5 tqfp 144 96 c lc4256v-3t100c 256 3.3 3 tqfp 100 64 c lc4256v-5t100c 256 3.3 5 tqfp 100 64 c lc4256v-75t100c 256 3.3 7.5 tqfp 100 64 c lc4384v lc4384v-35f256c 384 3.3 3.5 fpbga 256 192 c lc4384v-5f256c 384 3.3 5 fpbga 256 192 c lc4384v-75f256c 384 3.3 7.5 fpbga 256 192 c lc4384v-35t176c 384 3.3 3.5 tqfp 176 128 c lc4384v-5t176c 384 3.3 5 tqfp 176 128 c lc4384v-75t176c 384 3.3 7.5 tqfp 176 128 c lc4512v lc4512v-35f256c 512 3.3 3.5 fpbga 256 208 c lc4512v-5f256c 512 3.3 5 fpbga 256 208 c lc4512v-75f256c 512 3.3 7.5 fpbga 256 208 c lc4512v-35t176c 512 3.3 3.5 tqfp 176 128 c lc4512v-5t176c 512 3.3 5 tqfp 176 128 c lc4512v-75t176c 512 3.3 7.5 tqfp 176 128 c ispmach 4000zc (zero power, 1.8v) commercial devices 1 device part number macrocells voltage t pd pa ck ag e pin/ball count i/o grade lc4032zc lc4032zc-35t48c 32 1.8 3.5 tqfp 48 32 c lc4032zc-5t48c 32 1.8 5 tqfp 48 32 c lc4032zc-75t48c 32 1.8 7.5 tqfp 48 32 c 1. preliminary information. ispmach 4000c (1.8v) industrial devices f amily part number macrocells voltage t pd pa ck ag e pin/ball count i/o grade lc4032c lc4032c-5t48i 32 1.8 5 tqfp 48 32 i lc4032c-75t48i 32 1.8 7.5 tqfp 48 32 i lc4032c-10t48i 32 1.8 10 tqfp 48 32 i lc4032c-5t44i 32 1.8 5 tqfp 44 30 i lc4032c-75t44i 32 1.8 7.5 tqfp 44 30 i lc4032c-10t44i 32 1.8 10 tqfp 44 30 i ispmach 4000v (3.3v) commercial devices (cont.) device part number macrocells voltage t pd pa ck ag e pin/ball count i/o grade
lattice semiconductor ispmach 4000v/b/c/z family data sheet 70 lc4064c lc4064c-5t100i 64 1.8 5 tqfp 100 64 i lc4064c-75t100i 64 1.8 7.5 tqfp 100 64 i lc4064c-10t100i 64 1.8 10 tqfp 100 64 i lc4064c-5t48i 64 1.8 5 tqfp 48 32 i lc4064c-75t48i 64 1.8 7.5 tqfp 48 32 i lc4064c-10t48i 64 1.8 10 tqfp 48 32 i lc4064c-5t44i 64 1.8 5 tqfp 44 30 i lc4064c-75t44i 64 1.8 7.5 tqfp 44 30 i lc4064c-10t44i 64 1.8 10 tqfp 44 30 i lc4128c lc4128c-5t128i 128 1.8 5 tqfp 128 92 i lc4128c-75t128i 128 1.8 7.5 tqfp 128 92 i lc4128c-10t128i 128 1.8 10 tqfp 128 92 i lc4128c-5t100i 128 1.8 5 tqfp 100 64 i lc4128c-75t100i 128 1.8 7.5 tqfp 100 64 i lc4128c-10t100i 128 1.8 10 tqfp 100 64 i lc4256c lc4256c-5f256ai 256 1.8 5 fpbga 256 128 i lc4256c-75f256ai 256 1.8 7.5 fpbga 256 128 i lc4256c-10f256ai 256 1.8 10 fpbga 256 128 i lc4256c-5f256bi 256 1.8 5 fpbga 256 160 i lc4256c-75f256bi 256 1.8 7.5 fpbga 256 160 i lc4256c-10f256bi 256 1.8 10 fpbga 256 160 i lc4256c-5t176i 256 1.8 5 tqfp 176 128 i lc4256c-75t176i 256 1.8 7.5 tqfp 176 128 i lc4256c-10t176i 256 1.8 10 tqfp 176 128 i lc4256c-5t100i 256 1.8 5 tqfp 100 64 i lc4256c-75t100i 256 1.8 7.5 tqfp 100 64 i lc4256c-10t100i 256 1.8 10 tqfp 100 64 i lc4384c lc4384c-5f256i 384 1.8 5 fpbga 256 192 i lc4384c-75f256i 384 1.8 7.5 fpbga 256 192 i lc4384c-10f256i 384 1.8 10 fpbga 256 192 i lc4384c-5t176i 384 1.8 5 tqfp 176 128 i lc4384c-75t176i 384 1.8 7.5 tqfp 176 128 i lc4384c-10t176i 384 1.8 10 tqfp 176 128 i lc4512c lc4512c-5f256i 512 1.8 5 fpbga 256 208 i lc4512c-75f256i 512 1.8 7.5 fpbga 256 208 i lc4512c-10f256i 512 1.8 10 fpbga 256 208 i lc4512c-5t176i 512 1.8 5 tqfp 176 128 i lc4512c-75t176i 512 1.8 7.5 tqfp 176 128 i lc4512c-10t176i 512 1.8 10 tqfp 176 128 i ispmach 4000c (1.8v) industrial devices (cont.) f amily part number macrocells voltage t pd pa ck ag e pin/ball count i/o grade
lattice semiconductor ispmach 4000v/b/c/z family data sheet 71 ispmach 4000b (2.5v) industrial devices f amily part number macrocells voltage t pd pa ck ag e pin/ball count i/o grade lc4032b lc4032b-5t48i 32 2.5 5 tqfp 48 32 i lc4032b-75t48i 32 2.5 7.5 tqfp 48 32 i lc4032b-10t48i 32 2.5 10 tqfp 48 32 i lc4032b-5t44i 32 2.5 5 tqfp 44 30 i lc4032b-75t44i 32 2.5 7.5 tqfp 44 30 i lc4032b-10t44i 32 2.5 10 tqfp 44 30 i lc4064b lc4064b-5t100i 64 2.5 5 tqfp 100 64 i lc4064b-75t100i 64 2.5 7.5 tqfp 100 64 i lc4064b-10t100i 64 2.5 10 tqfp 100 64 i lc4064b-5t48i 64 2.5 5 tqfp 48 32 i lc4064b-75t48i 64 2.5 7.5 tqfp 48 32 i lc4064b-10t48i 64 2.5 10 tqfp 48 32 i lc4064b-5t44i 64 2.5 5 tqfp 44 30 i LC4064B-75T44I 64 2.5 7.5 tqfp 44 30 i lc4064b-10t44i 64 2.5 10 tqfp 44 30 i lc4128b lc4128b-5t128i 128 2.5 5 tqfp 128 92 i lc4128b-75t128i 128 2.5 7.5 tqfp 128 92 i lc4128b-10t128i 128 2.5 10 tqfp 128 92 i lc4128b-5t100i 128 2.5 5 tqfp 100 64 i lc4128b-75t100i 128 2.5 7.5 tqfp 100 64 i lc4128b-10t100i 128 2.5 10 tqfp 100 64 i lc4256b lc4256b-5f256ai 256 2.5 5 fpbga 256 128 i lc4256b-75f256ai 256 2.5 7.5 fpbga 256 128 i lc4256b-10f256ai 256 2.5 10 fpbga 256 128 i lc4256b-5f256bi 256 2.5 5 fpbga 256 160 i lc4256b-75f256bi 256 2.5 7.5 fpbga 256 160 i lc4256b-10f256bi 256 2.5 10 fpbga 256 160 i lc4256b-5t176i 256 2.5 5 tqfp 176 128 i lc4256b-75t176i 256 2.5 7.5 tqfp 176 128 i lc4256b-10t176i 256 2.5 10 tqfp 176 128 i lc4256b-5t100i 256 2.5 5 tqfp 100 64 i lc4256b-75t100i 256 2.5 7.5 tqfp 100 64 i lc4256b-10t100i 256 2.5 10 tqfp 100 64 i lc4384b lc4384b-5f256i 384 2.5 5 fpbga 256 192 i lc4384b-75f256i 384 2.5 7.5 fpbga 256 192 i lc4384b-10f256i 384 2.5 10 fpbga 256 192 i lc4384b-5t176i 384 2.5 5 tqfp 176 128 i lc4384b-75t176i 384 2.5 7.5 tqfp 176 128 i lc4384b-10t176i 384 2.5 10 tqfp 176 128 i
lattice semiconductor ispmach 4000v/b/c/z family data sheet 72 lc4512b lc4512b-5f256i 512 2.5 5 fpbga 256 208 i lc4512b-75f256i 512 2.5 7.5 fpbga 256 208 i lc4512b-10f256i 512 2.5 10 fpbga 256 208 i lc4512b-5t176i 512 2.5 5 tqfp 176 128 i lc4512b-75t176i 512 2.5 7.5 tqfp 176 128 i lc4512b-10t176i 512 2.5 10 tqfp 176 128 i ispmach 4000v (3.3v) industrial devices f amily part number macrocells voltage t pd pa ck ag e pin/ball count i/o grade lc4032v lc4032v-5t48i 32 3.3 5 tqfp 48 32 i lc4032v-75t48i 32 3.3 7.5 tqfp 48 32 i lc4032v-10t48i 32 3.3 10 tqfp 48 32 i lc4032v-5t44i 32 3.3 5 tqfp 44 30 i lc4032v-75t44i 32 3.3 7.5 tqfp 44 30 i lc4032v-10t44i 32 3.3 10 tqfp 44 30 i lc4064v lc4064v-5t100i 64 3.3 5 tqfp 100 64 i lc4064v-75t100i 64 3.3 7.5 tqfp 100 64 i lc4064v-10t100i 64 3.3 10 tqfp 100 64 i lc4064v-5t48i 64 3.3 5 tqfp 48 32 i lc4064v-75t48i 64 3.3 7.5 tqfp 48 32 i lc4064v-10t48i 64 3.3 10 tqfp 48 32 i lc4064v-5t44i 64 3.3 5 tqfp 44 30 i lc4064v-75t44i 64 3.3 7.5 tqfp 44 30 i lc4064v-10t44i 64 3.3 10 tqfp 44 30 i lc4128v lc4128v-5t144i 128 3.3 5 tqfp 144 96 i lc4128v-75t144i 128 3.3 7.5 tqfp 144 96 i lc4128v-10t144i 128 3.3 10 tqfp 144 96 i lc4128v-5t128i 128 3.3 5 tqfp 128 92 i lc4128v-75t128i 128 3.3 7.5 tqfp 128 92 i lc4128v-10t128i 128 3.3 10 tqfp 128 92 i lc4128v-5t100i 128 3.3 5 tqfp 100 64 i lc4128v-75t100i 128 3.3 7.5 tqfp 100 64 i lc4128v-10t100i 128 3.3 10 tqfp 100 64 i ispmach 4000b (2.5v) industrial devices (cont.) f amily part number macrocells voltage t pd pa ck ag e pin/ball count i/o grade
lattice semiconductor ispmach 4000v/b/c/z family data sheet 73 lc4256v lc4256v-5f256ai 256 3.3 5 fpbga 256 128 i lc4256v-75f256ai 256 3.3 7.5 fpbga 256 128 i lc4256v-10f256ai 256 3.3 10 fpbga 256 128 i lc4256v-5f256bi 256 3.3 5 fpbga 256 160 i lc4256v-75f256bi 256 3.3 7.5 fpbga 256 160 i lc4256v-10f256bi 256 3.3 10 fpbga 256 160 i lc4256v-5t176i 256 3.3 5 tqfp 176 128 i lc4256v-75t176i 256 3.3 7.5 tqfp 176 128 i lc4256v-10t176i 256 3.3 10 tqfp 176 128 i lc4256v-5t144i 256 3.3 5 tqfp 144 96 i lc4256v-75t144i 256 3.3 7.5 tqfp 144 96 i lc4256v-10t144i 256 3.3 10 tqfp 144 96 i lc4256v-5t100i 256 3.3 5 tqfp 100 64 i lc4256v-75t100i 256 3.3 7.5 tqfp 100 64 i lc4256v-10t100i 256 3.3 10 tqfp 100 64 i lc4384v lc4384v-5f256i 384 3.3 5 fpbga 256 192 i lc4384v-75f256i 384 3.3 7.5 fpbga 256 192 i lc4384v-10f256i 384 3.3 10 fpbga 256 192 i lc4384v-5t176i 384 3.3 5 tqfp 176 128 i lc4384v-75t176i 384 3.3 7.5 tqfp 176 128 i lc4384v-10t176i 384 3.3 10 tqfp 176 128 i lc4512v lc4512v-5f256i 512 3.3 5 fpbga 256 208 i lc4512v-75f256i 512 3.3 7.5 fpbga 256 208 i lc4512v-10f256i 512 3.3 10 fpbga 256 208 i lc4512v-5t176i 512 3.3 5 tqfp 176 128 i lc4512v-75t176i 512 3.3 7.5 tqfp 176 128 i lc4512v-10t176i 512 3.3 10 tqfp 176 128 i ispmach 4000v (3.3v) automotive devices device part number macrocells voltage t pd pa ck ag e pin/ball count i/o grade lc4032v lc4032v-75t48e 32 3.3 7.5 tqfp 48 32 e lc4032v-75t44e 32 3.3 7.5 tqfp 44 30 e lc4064v lc4064v-75t100e 64 3.3 7.5 tqfp 100 64 e lc4064v-75t48e 64 3.3 7.5 tqfp 48 32 e lc4064v-75t44e 64 3.3 7.5 tqfp 44 30 e lc4128v lc4128v-75t144e 128 3.3 7.5 tqfp 144 96 e lc4128v-75t128e 128 3.3 7.5 tqfp 128 92 e lc4128v-75t100e 128 3.3 7.5 tqfp 100 64 e lc4256v lc4256v-75t176e 256 3.3 7.5 tqfp 176 128 e lc4256v-75t144e 256 3.3 7.5 tqfp 144 96 e lc4256v-75t100e 256 3.3 7.5 tqfp 100 64 e ispmach 4000v (3.3v) industrial devices (cont.) f amily part number macrocells voltage t pd pa ck ag e pin/ball count i/o grade
lattice semiconductor ispmach 4000v/b/c/z family data sheet 74 for further information in addition to this data sheet, the following technical notes may be helpful when designing with the ispmach 4000v/b/c/z family: ? ispmach 4000 timing model design and usage guidelines (tn1004) ? ispmach 4000v/b/c power consumption (tn1005) ? low power design guide (tn1042)

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